km29u128t Samsung Semiconductor, Inc., km29u128t Datasheet - Page 5

• Manufacturer Part Number: km29u128t
• Description: 16m X 8 Bit Nand Flash Memory
• Manufacturer: Samsung Semiconductor, Inc.

PIN DESCRIPTION
Command Latch Enable(CLE)
Address Latch Enable(ALE)
Chip Enable(CE)
Write Enable(WE)
Read Enable(RE)
Spare Area Enable(SE)
I/O Port : I/O 0 ~ I/O 7
Write Protect(WP)
Ready/Busy(R/B)
KM29U128T, KM29U128IT
The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched
into the command register through the I/O ports on the rising edge of the WE signal.
The ALE input controls the path activation for address and input data to the internal address/data register.
Addresses are latched on the rising edge of WE with ALE high, and input data is latched when ALE is low.
The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode.
However, when the device is in the busy state during program or erase, CE high is ignored, and does not return the device to
standby mode.
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge
of RE which also increments the internal column address counter by one.
The SE input controls the spare area selection when SE is high, the device is deselected the spare area during Read1, Sequential
data input and Page Program.
The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z
when the chip is deselected or when the outputs are disabled.
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when
the WP pin is active low.
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is
in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip
is deselected or when outputs are disabled.
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FLASH MEMORY