km29u128t Samsung Semiconductor, Inc., km29u128t Datasheet - Page 20

• Manufacturer Part Number: km29u128t
• Description: 16m X 8 Bit Nand Flash Memory
• Manufacturer: Samsung Semiconductor, Inc.

DEVICE OPERATION
PAGE READ
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00H to the command reg-
ister along with three address cycles. Once the command is latched, it does not need to be written for the following page read opera-
tion. Three types of operations are available : random read, serial page read and sequential row read.
The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are trans-
ferred to the data registers in less than 10 s(tR). The system controller can detect the completion of this data transfer(tR) by analyz-
ing the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially
pulsing RE. High to low transitions of the RE clock output the data stating from the selected column address up to the last column
address(column 511 or 527 depending on the state of SE pin).
After the data of last column address is clocked out, the next page is automatically selected for sequential row read.
Waiting 10 s again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. The
way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of bytes
512 to 527 may be selectively accessed by writing the Read2 command with SE pin low. Addresses A
of the spare area while addresses A
mented for sequential row read as in Read1 operation and spare sixteen bytes of each page may be sequentially read. The Read1
command(00H/01H) is needed to move the pointer back to the main area. Figures 3 thru 6 show typical sequence and timings for
each read operation.
KM29U128T, KM29U128IT
Figure 3. Read1 Operation
CLE
CE
WE
ALE
R/B
RE
I/O
0
~
7
* After data access on 2nd half array by 01H command, the start pointer is automatically moved to 1st half
array (00H) at next cycle.
00H
A
0
Start Add.(3Cycle)
~ A
7
& A
4
9
to A
~ A
7
23
are ignored. Unless the operation is aborted, the page address is automatically incre-
1st half array
t
R
(00H Command)
Data Field
2st half array
20
Spare Field
1st half array
Data Output(Sequential)
(01H Command)*
Data Field
FLASH MEMORY
0
to A
2st half array
3
set the starting address
Spare Field