hdd128m72d18rpw ETC-unknow, hdd128m72d18rpw Datasheet
hdd128m72d18rpw
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hdd128m72d18rpw Summary of contents
Page 1
... EEPROM in 8-pin TSSOP package on a 184-pin glass-epoxy. Four 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each DDR SDRAM. The HDD128M72D18RPW is a DIMM( Dual in line Memory Module) .Synchronous design allows precise cycle c ontrol with the use of system clock. Data I/O transactions are possible on both edges of DQS ...
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... SDA 122 92 SCL 123 PIN Address input VDD VDDQ VREF Check Bit VDDSPD VSS Data-in Mask SA0~SA2 Clock input SDA SCL VDDID NC 2 HDD128M72D18RPW Back PIN Front PIN V 124 V 154 SS SS DQ4 125 A6 155 DQ5 126 DQ28 156 V 127 DQ29 157 ...
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... HANBit A0-A12 URL : www.hbe.co.kr REV 1.0 (January. 2005) Functional Block Diagram 3 HDD128M72D18RPW HANBit Electronics Co.,Ltd. ...
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... WRITE access sampled on both edges of DQS. DM pins include dummy loading internally, to matches the DQ and DQS load-ing. Data inputs/outputs are multiplexed on the same pins. DQ Power Supply : +2.5V ± 0.2V. Power Supply : +2.5V ± 0.2V (device specific). DQ Ground. SSTL_2 reference voltage. Serial EEPROM Power Supply : 3.3v VDD identification Flag 4 HDD128M72D18RPW HANBit Electronics Co.,Ltd. ...
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... AC noise and DC offset on V REF REF 3nH system supply for signal termination resistors, is expected to be set equal REF envelop that has been bandwidth limited to 200MHZ. REF 5 HDD128M72D18RPW RATING -0.5 ~ 3.6 -1.0 ~ 3.6 -0.5 ~ 3.6 -55 ~ +150 1 component 50 MAX UNIT 2 ...
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... STMBOL V (AC (AC (AC (AC the transmitting device and must track variations in the DC level of the same DDQ 6 HDD128M72D18RPW MIN MAX -13B Unit (DDR266@CL=2.5) 2010 mA 2280 ...
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... 0.45 - DQSQ t 0.9 1.1 0.9 RPRE t 0.4 0.6 0.4 RPST t 0.75 1.25 0.75 DQSS WPRES t 0.25 0.25 WPREH t 0.2 0.2 DSS t 0.2 0.2 DSH t 0.35 0.35 DQSH t 0.35 0.35 DQSL t 0.9 0.9 DSC t 0.75 0 0.75 0 0.8 1 HDD128M72D18RPW DDR266B@CL=2.5 UNIT -13A -13B MAX MIN MAX 120K 45 120K 7 0.55 0.45 0.55 t 0.55 0.45 0.55 t +0.75 -0.75 +0.75 ns +0.75 -0.75 +0.75 ns +0.5 - +0.5 ns 1.1 0.9 1.1 t 0.6 0.4 0 ...
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... QHS QHS CLmin CLmin - t t CHmin CHmin t 0.55 QHS t 0.4 0.6 0.4 WPST t 18 RAP ( DAL ( HDD128M72D18RPW 1.0 ns +0.75 -0.75 +0.75 ns +0.75 -0.75 +0.75 ns 0 4.5 1.0 4 0.7 5 1.5 0.67 1 0 2 200 QHS ...
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... TDH 0 +75 +150 TDH 0 +50 +100 TYPICAL RANGE MINIMUM (V/NS) (V/NS) 1.2 ~ 2.5 1.0 1.2 ~ 2.5 1.0 TYPICAL RANGE MINIMUM (V/NS) (V/NS) 1.2 ~ 2.5 0.7 1.2 ~ 2.5 0.7 DDR333 MIN MAX TBD TBD 9 HDD128M72D18RPW DDR266 MIN MAX Units TBD TBD V/ns UNITS NOTES UNITS NOTES UNITS NOTES MAXIMUM ...
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... For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR266B at CL=2.5 and tCK=7.5ns tDAL = ( 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3) tDAL = 5 clocks URL : www.hbe.co.kr REV 1.0 (January. 2005) 1.0 V/ns 0.5 V/ns and < 1.0 V/ns 10 HDD128M72D18RPW HANBit Electronics Co.,Ltd. ...
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... VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions. m. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions through the DC region must be monotony. URL : www.hbe.co.kr REV 1.0 (January. 2005) HDD128M72D18RPW 11 HANBit Electronics Co.,Ltd. ...
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... (V=Valid, X=Don't care, H=Logic high, L=Logic low) after the end of burst HDD128M72D18RPW BA A10/ / code code Row address ...
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... HANBit PACKAGING INFORMATION Unit : mm <Front– Side > < Rear – Side > PCB Thickness : 1.27 ± 0.08 mm *** URL : www.hbe.co.kr REV 1.0 (January. 2005) HDD128M72D18RPW 133.35 ± 0.20 A 133.35 ± 0.20 13 30.48± 0.20 B 30.48± 0.20 HANBit Electronics Co.,Ltd. ...
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... HDD128M72D18RPW-13B 1024MByte URL : www.hbe.co.kr REV 1.0 (January. 2005) Org. Package Ref. 184PIN 128M DIMM 184PIN 128M DIMM 184PIN 128M DIMM 14 HDD128M72D18RPW Vcc MODE MAX.frq DDR 166MHz/CL2 2.5V Registered DDR333 DDR 133MHz/CL2 2.5V Registered DDR266 DDR 133MHz/CL2.5 2.5V Registered DDR266 HANBit Electronics Co.,Ltd. ...