k4h2g0638a-uc Samsung Semiconductor, Inc., k4h2g0638a-uc Datasheet
k4h2g0638a-uc
Related parts for k4h2g0638a-uc
k4h2g0638a-uc Summary of contents
Page 1
... DDR SDRAM stacked 2Gb A-die (x4) Stacked 2Gb A-die SDRAM Specification 66 TSOP-II with Pb-Free INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS " ...
Page 2
... Absolute Maximum Rating .......................................................................................................9 11.0 DC Operating Conditions ..........................................................................................................9 12.0 DDR SDRAM Spec Items & Test Conditions .........................................................................10 13.0 Input/Output Capacitance ......................................................................................................10 14.0 Detailed test condition for DDR SDRAM IDD1 & IDD7A ......................................................11 15.0 DDR SDRAM IDD spec table ..................................................................................................12 15.1 Current Calculation table 16.0 AC Operating Conditions .......................................................................................................13 17.0 AC Overshoot/Undershoot specification for Address and Control Pins ...........................13 18.0 Overshoot/Undershoot specification for Data, Strobe and Mask Pins...............................14 19.0 AC Timming Parameters & ...
Page 3
... DDR SDRAM stacked 2Gb A-die (x4) Revision History Revision Month Year 0.0 June 2005 - First version for internal review Preliminary DDR SDRAM History Rev. 0.0 June. 2005 ...
Page 4
... Maximum burst refresh cycle : 8 • 66pin TSOP II Pb-free package • RoHS compliant 2.0 Ordering Information Part No. Org. K4H2G0638A-UC/LCC K4H2G0638A-UC/LB3 st. 512M x 4 K4H2G0638A-UC/LA2 K4H2G0638A-UC/LB0 3.0 Operating Frequencies CC(DDR400@CL=3) Speed @CL2 - Speed @CL2.5 166MHz Speed @CL3 200MHz CL-tRCD-tRP 3-3-3 Max Freq. Interface CC(DDR400@CL=3) B3(DDR333@CL=2 ...
Page 5
... DDR SDRAM stacked 2Gb A-die (x4) 4.0 Pin Description DDQ SSQ DDQ SSQ DDQ CAS RAS CS0 CS1 AP Organization st. 512Mx4 DM is internally loaded to match DQ and DQS identically. ...
Page 6
... DDR SDRAM stacked 2Gb A-die (x4) 5.0 Package Physical Dimension #66 #1 (1.50) (0.71) NOTE REFERENCE ASS’Y OUT QUALITY 6.0 Block Diagram CK,CK,CAS RAS,WE,DM CKE1,CS1 CKE0,CS0 #34 #33 22.22±0.10 (10×) 0.65TYP 0.30±0.08 0.65±0.08 (10×) 66pin TSOPII / Package dimension 256Mx4 256Mx4 I/O0-I/O3,DQS A0-A13,BA0,BA1 st.512Mb x 4 Preliminary ...
Page 7
... DDR SDRAM stacked 2Gb A-die (x4) 7.0 Input/Output Function Description SYMBOL TYPE Clock : CK and CK are differential clock inputs. All address and control input signals are sam- CK, CK Input pled on the positive edge of CK and negative edge of CK. Output (read) data is referenced to both edges of CK. Internal clock signals are derived from CK/CK. ...
Page 8
... UDM/LDM(x16 only) sampled at the rising and falling edges of the UDQS/LDQS and Data-in are masked at the both edges (Write UDM/LDM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM. (V=Valid, X=Donct Care, H=Logic High, L=Logic Low) ...
Page 9
... DDR SDRAM stacked 2Gb A-die (x4) st. 128M x 4Bit x 4 Banks Double Data Rate SDRAM 9.0 General Description The K4H2G0638A is 2,147,483,648 bits of double data rate synchronous DRAM organized as 4x134,217,728 words by 4bits, fabricated / with SAMSUNGcs high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 400Mb/s per pin ...
Page 10
... DDR SDRAM stacked 2Gb A-die (x4) 12.0 DDR SDRAM Spec Items & Test Conditions Operating current - One bank Active-Precharge; tRC=tRCmin; tCK=10ns for DDR200, tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400; DQ,DM and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. ...
Page 11
... DDR SDRAM stacked 2Gb A-die (x4) 14.0 Detailed test condition for DDR SDRAM IDD1 & IDD7A IDD1 : Operating current: One bank operation 1. Typical Case: For DDR200,266,333: Vdd = 2.5V, T=25qC; For DDR400: Vdd=2.6V,T=25qC Worst Case : Vdd = 2.7V, T= 10qC 2. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle ...
Page 12
... Normal 30 IDD6 Low power 10 IDD7A 430 15.1 Current Calculation table 1st Comp. Condition(Active) IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7A st. 512Mx4 (K4H2G0638A) 150 130 170 150 105 95 210 190 210 190 280 260 ...
Page 13
... DDR SDRAM stacked 2Gb A-die (x4) 16.0 AC Operating Conditions Parameter/Condition Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals. Input Differential Voltage, CK and /CK inputs Input Crossing Point Voltage, CK and /CK inputs Note : 1. VID is the magnitude of the difference between the input level on CK and the input level on /CK. ...
Page 14
... DDR SDRAM stacked 2Gb A-die (x4) 18.0 Overshoot/Undershoot specification for Data, Strobe and Mask Pins Parameter Maximum peak amplitude allowed for overshoot Maximum peak amplitude allowed for undershoot The area between the overshoot signal and VDD must be less than or equal to The area between the undershoot signal and GND must be less than or equal to ...
Page 15
... DDR SDRAM stacked 2Gb A-die (x4) 19.0 AC Timming Parameters & Specifications Parameter Symbol Row cycle time Refresh row cycle time Row active time RAS to CAS delay tRCD Row precharge time Row active to Row active delay tRRD Write recovery time Last data in to Read command tWTR CL=2 ...
Page 16
... DDR SDRAM stacked 2Gb A-die (x4) 20.0 System Characteristics for DDR SDRAM The following specification parameters are required in systems using DDR333, DDR266 & DDR200 devices to ensure proper system performance. these characteristics are for system simulation purposes and are guaranteed by design. Table 1 : Input Slew Rate for DQ, DQS, and DM ...
Page 17
... DQS will be transitioning from High logic LOW previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 14. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device. 15. For command/address input slew rate t1.0 V/ns 16 ...
Page 18
... DDR SDRAM stacked 2Gb A-die (x4) Component Notes 17. For CK & CK slew rate t1.0 V/ns 18. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. 19. Slew Rate is measured between VOH(ac) and VOL(ac). 20. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH) ...
Page 19
... DDR SDRAM stacked 2Gb A-die (x4) 22.0 System Notes a. Pullup slew rate is characteristized under the test conditions as shown in Figure 2. Output Figure 2 : Pullup slew rate test load b. Pulldown slew rate is measured under the test conditions shown in Figure 3. Output Figure 3 : Pulldown slew rate test load c ...
Page 20
... DDR SDRAM Output Driver V-I Characteristics DDR SDRAM Output driver characteristics are defined for full and half strength operation as selected by the EMRS bit A1. Figures 3 and 4 show the driver characteristics graphically, and tables 8 and 9 show the same data in tabular format suitable for input into simulation tools ...
Page 21
... DDR SDRAM stacked 2Gb A-die (x4) Pulldown Current (mA) Voltage Typical Typical (V) Low High 0.1 6.0 6.8 0.2 12.2 13.5 0.3 18.1 20.1 0.4 24.1 26.6 0.5 29.8 33.0 0.6 34.6 39.1 0.7 39.4 44.2 0.8 43.7 49.8 0.9 47.5 55.2 1.0 51.3 60.3 1.1 54.1 65.2 1.2 56.2 69.9 1.3 57.9 74.2 1.4 59.3 78.4 1.5 60.1 82.3 1.6 60.5 85.9 1.7 61.0 89.1 1.8 61.5 92.2 1.9 62.0 95.3 2.0 62.5 97.2 2.1 62.9 99.1 2.2 63.3 100.9 2.3 63.8 101.9 2.4 64.1 102.8 2.5 64.6 103.8 2.6 64.8 104.6 2.7 65.0 105.4 Table 8. Full Strength Driver Characteristics Typical Minimum Maximum Low 4.6 9.6 -6.1 9.2 18.2 -12.2 13.8 26.0 -18.1 18.4 33.9 -24.0 23.0 41.8 -29.8 27.7 49.4 -34.3 32.2 56.8 -38.1 36.8 63.2 -41.1 39.6 69.9 -41.8 42.6 76.3 -46.0 44.8 82.5 -47.8 46.2 88.3 -49.2 47.1 93.8 -50.0 47.4 99.1 -50.5 47.7 103.8 -50.7 48.0 108.4 -51.0 48.4 112.1 -51.1 48.9 115.9 -51.3 49.1 119.6 -51.5 49.4 123.3 -51.6 49.6 126.5 -51.8 49.8 129.5 -52.0 49.9 132.4 -52.2 50.0 135.0 -52.3 50.2 137.3 -52.5 50.4 139.2 -52.7 50.5 140.8 -52.8 Preliminary ...
Page 22
... DDR SDRAM stacked 2Gb A-die (x4 0.0 Pullup Characteristics for Weak Output Driver 0.0 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 Pulldown Characteristics for Weak Output Driver Figure 4. I/V characteristics for input/output buffers:Pull up(above) and pull down(below) 1.0 2.0 1.0 2.0 Preliminary DDR SDRAM Maximum Typical High ...
Page 23
... DDR SDRAM stacked 2Gb A-die (x4) Pulldown Current (mA) Voltage Typical Typical (V) Low High 0.1 3.4 3.8 0.2 6.9 7.6 0.3 10.3 11.4 0.4 13.6 15.1 0.5 16.9 18.7 0.6 19.6 22.1 0.7 22.3 25.0 0.8 24.7 28.2 0.9 26.9 31.3 1.0 29.0 34.1 1.1 30.6 36.9 1.2 31.8 39.5 1.3 32.8 42.0 1.4 33.5 44.4 1.5 34.0 46.6 1.6 34.3 48.6 1.7 34.5 50.5 1.8 34.8 52.2 1.9 35.1 53.9 2.0 35.4 55.0 2.1 35.6 56.1 2.2 35.8 57.1 2.3 36.1 57.7 2.4 36.3 58.2 2.5 36.5 58.7 2.6 36.7 59.2 2.7 36.8 59.6 Table 9. Weak Driver Characteristics Typical Minimum Maximum Low 2.6 5.0 -3.5 5.2 9.9 -6.9 7.8 14.6 -10.3 10.4 19.2 -13.6 13.0 23.6 -16.9 15.7 28.0 -19.4 18.2 32.2 -21.5 20.8 35.8 -23.3 22.4 39.5 -24.8 24.1 43.2 -26.0 25.4 46.7 -27.1 26.2 50.0 -27.8 26.6 53.1 -28.3 26.8 56.1 -28.6 27.0 58.7 -28.7 27.2 61.4 -28.9 27.4 63.5 -28.9 27.7 65.6 -29.0 27.8 67.7 -29.2 28.0 69.8 -29.2 28.1 71.6 -29.3 28.2 73.3 -29.5 28.3 74.9 -29.5 28.3 76.4 -29.6 28.4 77.7 -29.7 28.5 78.8 -29.8 28.6 79.7 -29.9 Preliminary DDR SDRAM pullup Current (mA) Typical Minimum Maximum High -4.3 -2.6 -5.0 -8.2 -5.2 -9.9 -12.0 -7.8 -14.6 -15.7 -10.4 -19.2 -19.3 -13.0 -23.6 -22.9 -15.7 -28.0 -26.5 -18.2 -32.2 -30.1 -20.4 -35.8 -33.6 -21.6 -39.5 -37.1 -21.9 -43.2 -40.3 -22.1 -46.7 -43.1 -22.2 -50.0 -45.8 -22.3 -53.1 -48.4 -22.4 -56.1 -50.7 -22.6 -58.7 -52.9 -22.7 -61.4 -55.0 -22.7 -63.5 -56.8 -22.8 -65.6 -58.7 -22.9 -67.7 -60.0 -22.9 -69.8 -61.2 -23.0 -71.6 -62.4 -23.0 -73.3 -63.1 -23.1 -74.9 -63.8 -23.2 -76.4 -64.4 -23.2 -77.7 -65.1 -23.3 -78.8 -65.8 -23.3 -79.7 Rev. 0.0 June. 2005 ...