m366s3323dts Samsung Semiconductor, Inc., m366s3323dts Datasheet - Page 6

• Manufacturer Part Number: m366s3323dts
• Description: 32mx64 Sdram Dimm Based On 16mx8, 4banks, 4k Refresh, 3.3v Synchronous Drams With Spd
• Manufacturer: Samsung Semiconductor, Inc.

OPERATING AC PARAMETER
AC OPERATING TEST CONDITIONS
(AC operating conditions unless otherwise noted)
Notes :
M366S3323DTS
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
Col. address to col. address delay
Number of valid output data
Output
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
(Fig. 1) DC output load circuit
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
and then rounding off to the next higher integer.
870
Parameter
Parameter
3.3V
1200
50pF
CAS latency=3
CAS latency=2
V
V
OH
OL
(DC) = 0.4V, I
(DC) = 2.4V, I
(V
t
t
t
t
t
t
t
t
t
RAS
RRD
RCD
t
CCD
Symbol
t
RAS
RDL
DAL
CDL
BDL
RP
RC
DD
(min)
(min)
(max)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
= 3.3V
OL
OH
0.3V, T
= 2mA
= -2mA
- 7C
15
15
15
45
60
A
PC133/PC100 Unbuffered DIMM
= 0 to 70 C)
See Fig. 2
tr/tf = 1/1
2.4/0.4
Value
1.4
1.4
Output
- 7A
15
20
20
45
65
2 CLK + tRP
Version
100
2
1
1
1
2
1
(Fig. 2) AC output load circuit
- 1H
20
20
20
50
70
Z0 = 50
Rev. 0.1 Sept. 2001
-1L
20
20
20
50
70
Unit
CLK
CLK
CLK
CLK
ns
ns
ns
ns
us
ns
ea
Vtt = 1.4V
Unit
-
50
ns
50pF
V
V
V
Note
2,5
1
1
1
1
1
5
2
2
3
4