am53c94 Advanced Micro Devices, am53c94 Datasheet - Page 36

• Manufacturer Part Number: am53c94
• Description: High Performance Scsi Controller
• Manufacturer: Advanced Micro Devices

Terminate Steps Command
(Command Code 24H/A4H)
The Terminate Steps Command is used by the target to
disconnect from the SCSI bus. This command consists
of three steps. The first step consists of sending one
status byte by the target in the Status Phase. The sec-
ond step consists of sending one message byte by the
target in the Message In Phase. As the third step the tar-
get disconnects from the SCSI bus. Successful Opera-
tion and Disconnected bits are set in the Interrupt Status
Register (INSTREG) 05H upon command completion. If
ATN signal is asserted by the initiator then Successful
Operation and Service Request bits are set in the IN-
STREG, the CMDREG is cleared and Terminate Steps
Command terminates without disconnecting.
Target Command Complete Steps Command
(Command Code 25H/A5H)
The Target Command Complete Steps Command is
used by the target to inform the initiator of a linked com-
mand completion. This command consists of two steps.
The first step consists of sending one status byte by the
target in the Status Phase. The second step consists of
sending one message byte by the target in the Message
In Phase. The Successful Operation bit is set in the In-
terrupt Status Register (INSTREG) 05H upon command
completion. If ATN signal is asserted by the initiator then
Successful Operation and Service Request bits are set
in the INSTREG, the CMDREG is cleared and Target
Command Complete Steps Command terminates
prematurely.
Disconnect Command
(Command Code 27H/A7H)
The Disconnect Command is used by the target to dis-
connect from the SCSI bus. All SCSI bus signals except
RSTC are released and the device returns to the Dis-
connected state. The RSTC signal is driven active for
about 25 micro seconds (depending on clock frequency
and clock factor). Interrupt is not generated to the micro-
processor.
Receive Message Steps Command
(Command Code 28H A8H)
The Receive Message Steps Command is used by the
target to request message bytes from the initiator. Dur-
ing this command the target receives the message
bytes from the initiator while the SCSI bus is in the Mes-
sage Out Phase. The Successful Operation bit is set in
the Interrupt Status Register (INSTREG) 05H upon
command completion. If ATN signal is asserted by the
initiator then Successful Operation and Service Re-
quest bits are set in the INSTREG, the CMDREG is
cleared. If a parity error is detected, the device ignores
the received message bytes until ATN signal is as-
serted, the Successful Operation bit is set in the IN-
STREG, and the CMDREG is cleared.
Receive Commands Command
(Command Code 29H/A9H)
The Receive Commands Command is used by the tar-
get to request the initiator for command bytes. During
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AMD
P R E L I M I N A R Y
Am53C94/Am53C96
this command the target receives the command bytes
from the initiator while the SCSI bus is in the Command
Phase. The Successful Operation bit is set in the Inter-
rupt Status Register (INSTREG) 05H upon command
completion. If ATN signal is asserted by the initiator then
Successful Operation and Service Request bits are set
in the INSTREG, the CMDREG is cleared and the com-
mand terminates prematurely. If a parity error is de-
tected, the device continues to receive command bytes
until the transfer is complete if the Abort on Command/
Data Parity Error (ACDPE) bit in the Control Register
(CNTLREG2) 0BH is reset. If the ACDPE bit is set, the
command is terminated immediately. The Parity Error
(PE) bit in the Status Register (STATREG) 04H is set
and CMDREG is cleared.
Receive Data Command
(Command Code 2AH/AAH)
The Receive Data Command is used by the target to re-
quest the initiator for data bytes. During this command
the target receives the data bytes from the initiator while
the SCSI bus is in the Data-Out Phase. The Successful
Operation bit is set in the Interrupt Status Register (IN-
STREG) 05H upon command completion. If ATN signal
is asserted by the initiator then Successful Operation
and Service Request bits are set in the INSTREG, the
CMDREG is cleared and the command terminates pre-
maturely. If a parity error is detected, the device contin-
ues to receive data bytes until the transfer is complete if
the Abort on Command/Data Parity Error (ACDPE) bit in
the Control Register (CNTLREG2) 0BH is reset. If the
ACDPE bit is set, the command is terminated immedi-
ately. The Parity Error (PE) bit in the Status Register
(STATREG) 04H is set and CMDREG is cleared.
Receive Command Steps Command
(Command Code 2BH/ABH)
The Receive Command Steps Command is used by the
target to request the initiator for command information
bytes. During this command the target receives the
command information bytes from the initiator while the
SCSI bus is in the Command Phase.
The target device determines the command byte length
from the first command byte. If an unknown length is re-
ceived, the Start Transfer Count Register (STCREG)
00H–01H is loaded with 5 and the Group Code Valid
(GCV) bit in the Status Register (STATREG) 04H is re-
set. If a valid length is received, the STCREG is loaded
with the appropriate value and the GCV bit in the
STATREG is set. If ATN signal is asserted by the initia-
tor then the Service Request bit is set in the INSTREG,
and the CMDREG is cleared If a parity error is detected,
the command is terminated prematurely and the
CMDREG is cleared.
DMA Stop Command (Command Code 04H/84H)
The DMA Stop Command is used by the target to allow
the microprocessor to discontinue data transfers due to
a lack of activity on the DMA channel. This command is
executed from the top of the command queue. If there is
a queued command waiting execution, it will be over-
written and the Illegal Operation Error (IOE) bit in the