am53c94 Advanced Micro Devices, am53c94 Datasheet - Page 13

• Manufacturer Part Number: am53c94
• Description: High Performance Scsi Controller
• Manufacturer: Advanced Micro Devices

PIN DESCRIPTION
Host Interface Signals
DMA 15–0
Data/DMA Bus
(Input/Output, Active High, Internal Pull-up)
The configuration of this bus depends on the Bus Mode
1–0 (BUSMD 1–0) inputs. When the device is config-
ured for a single bus operation, the host can access the
internal register set on the lower eight lines and the DMA
accesses can be made to the FIFO using entire bus.
When using the Byte Mode via the BHE and A0 inputs
the data can be transferred on either the upper or lower
half of the DMA 15–0 bus.
DMAP 1–0
Data/DMA Parity Bus
(Input/Output, Active High, Internal Pull-up)
These lines are odd parity for the DMA 15–0 bus. DMAP
1 is the parity for the upper half of the bus DMA 15–8 and
DMAP 0 is the parity for the lower half of the bus
DMA 7–0.
ALE [A3]
Address Latch Enable [Address 3]
(Input, Active High)
This is a dual function input. When the device is config-
ured for the dual bus mode (two buses, multiplexed and
byte control), this input acts as ALE. As ALE, this input
latches the address on the AD 7–0 bus on its Low going
edge. When the device is configured for all other bus
modes, this input acts as A3. As A3, this input is the third
bit of the address bus.
DMARD [A2]
DMA Read [Address 2]
(Input, Active Low [Active High])
This is a dual function input. When the device is config-
ured for the dual bus mode (two buses, multiplexed and
byte control), this input acts as DMARD. As DMARD,
this input is the read signal for the DMA 15–0 bus. When
the device is configured for all other bus modes, this in-
put acts as A2. As A2, this input is the second bit of the
address bus.
BHE [A1]
Bus High Enable [Address 1]
(Input, Active High)
This is a dual function input. When the device is config-
ured for the dual bus mode (two buses, multiplexed and
byte control), this input acts as BHE. As BHE, this input
works in conjunction with AS0 to indicate the lines on
which data transfer will take place. When the device is
configured for all other bus modes this input acts as A1.
As A1, this input is the first bit of the address bus.
P R E L I M I N A R Y
Am53C94/Am53C96
AS0 [A0]
Address Status [Address 0]
(Input, Active High)
This is a dual function input. When the device is config-
ured for the dual bus mode (two buses, multiplexed and
byte control), this input acts as AS0. As AS0, this input
works in conjunction with BHE to indicate the lines on
which data transfer will take place. When the device is
configured for all other bus modes, this input acts as A0.
As A0, this input is the zeroth bit of the address bus.
The following is the decoding for the BHE and AS0
DREQ
DMA Request
(Output, Active High, Hi-Z)
This output signal to the DMA controller will be active
during DMA read and write cycles. During a DMA read
cycle it will be active as long as there is a word (or a byte
in the byte mode) in the FIFO to be transferred to mem-
ory. During a DMA write cycle it will be active as long as
there is an empty space for a word (or a byte in the byte
mode) in the FIFO.
DACK
DMA Acknowledge
(Input, Active Low)
This input signal from the DMA controller will be active
during DMA read and write cycles. The DACK signal is
used to access the DMA FIFO only and should never be
active simultaneously with the CS signal, which ac-
cesses the registers only.
AD 7–0
Host Address Data Bus
(Input/Output, Active High, Internal Pull-up)
This bus is used only in the dual bus mode. This bus al-
lows the host processor to access the device’s internal
registers while the DMA bus is transferring data. When
using multiplexed bus, these lines can be used for ad-
dress and data. When using non multiplexed bus these
lines can be used for the data only.
inputs:
BHE
1
1
0
0
AS0
1
0
1
0
Bus Used
Upper Bus – DMA 15–8, DMAP 1
Full Bus – DMA 15–0, DMAP 1–0
Reserved
Lower Bus – DMA 7–0, DMAP 0
AMD
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