mt9v125 aptina, mt9v125 Datasheet - Page 7

• Manufacturer Part Number: mt9v125
• Description: 1/4-inch System-on-a-chip Soc Vga Ntsc And Pal Cmos Digital Image Sensor
• Manufacturer: aptina

Table 4:
PDF: 09005aef829db8a0/Source: 09005aef829dbfdb
MT9V125_LDS_2.fm - Rev. A 4/07 EN
A2, B1, B2, C1,
D8, C3, C6, F3,
A1, A8, E8 ,H1
C2, D2, E2, D1
F7, E7, B3, A3,
B4, A4, B5, A5
Assignment
Ball
H4
H2
D7
A6
G7
H8
H7
H6
G6
G8
A7
C7
B7
B6
B8
C8
E1
F8
F6
Ball Descriptions (continued)
Notes:
FRAME_VALID
LVDS_ENABLE
LINE_VALID
D
D
LVDS_NEG
LVDS_POS
DAC_NEG
D
DAC_POS
DAC_REF
DIN_CLK
V
D
OUT
OUT
VAAPIX
V
PIXCLK
OUT
Name
S
A
D
DD
IN
DD
V
V
DATA
GND
GND
[7:0]
AA
DD
_LSB0
_LSB1
DAC
[7:0]
PLL
1. ALL power pins (V
2. ALL ground pins (A
3. Inputs are not tolerant to signal voltages above 3.1V.
4. All unused inputs must be tied to GND or V
5. V
(nominal). Power pins cannot be floated.
floated.
AA
and VAAPIX must be tied to the same potential for proper operation.
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Input
Input
Input
Type
DD
GND
/V
MT9V125: 1/4-Inch VGA SOC Digital Image Sensor
Active HIGH: Enables the LVDS output port. Must be HIGH if LVDS is
to be used.
External data input port selectable at video encoder input.
D
Two-wire serial interface data I/O.
Pixel data output D
Sensor stand-alone mode output 0—typically left unconnected for
normal SOC operation.
Sensor stand-alone mode output 1—typically left unconnected for
normal SOC operation.
Active HIGH: FRAME_VALID (FV); indicates active frame.
Active HIGH: LINE_VALID (LV); indicates active pixel.
Pixel clock output.
Positive video DAC output in differential mode.
Video DAC output in single-ended mode.
Negative video DAC output in differential mode. Tie to GND in
single-ended mode.
External reference resistor for video DAC.
LVDS positive output.
LVDS negative output.
Analog ground.
Digital ground.
Analog power: 2.5–3.1V (2.8V nominal).
Pixel array analog power supply: 2.5–3.1V (2.8V nominal).
Digital power: 2.5–3.1V (2.8V nominal).
DAC power: 2.5–3.1V (2.8V nominal).
LVDS PLL power: 2.5–3.1V (2.8V nominal).
significant bit [LSB]). Data output [9:2] in sensor stand-alone mode
DD
/D
IN
DAC/V
GND
capture clock. (This clock must be synchronous to EXTCLK.)
) must be connected to ground. Ground pins cannot be
7
DD
PLL/V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
AA
/VAAPIX) must be connected to 2.8V
OUT
DD
7 (most significant bit [MSB]), D
.
Description
©2007 Micron Technology, Inc. All rights reserved.
Ball Assignments
OUT
0 (least