hys64t64020em-2.5-b2 Qimonda, hys64t64020em-2.5-b2 Datasheet - Page 4

• Manufacturer Part Number: hys64t64020em-2.5-b2
• Description: 214-pin Unbuffered Ddr2 Sdram Microdimm Modules Mdimm Sdram
• Manufacturer: Qimonda

1.2
The
module family are Micro-DIMM modules “MDIMMs” with 30
mm height based on DDR2 technology.
DIMMs
in64M × 64 (512MB) in organization and density, intended for
mounting into 214-pin connector sockets.
1) For detailed information regarding Product Type of Qimonda please see chapter "Product Type Nomenclature" of this datasheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example "PC2–6400M–666–12–A0" where
1) Green Product
2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
Rev. 1.10, 2008-03
09032007-YO3V-5RUJ
Product Type
PC2-6400 (6-6-6)
HYS64T64020EM-2.5-B2
PC2-5300 (4-4-4)
HYS64T64020EM-3-B2
PC2-5300 (5-5-5)
HYS64T64020EM-3S-B2
PC2-4200 (4-4-4)
HYS64T64020EM-3.7-B2
PC2-3200 (3-3-3)
HYS64T64020EM-5-B2
DIMM
Density
512MB
Product Type
HYS64T64020EM
6400M means Micro-DIMM modules with 6.40 GB/sec Module Bandwidth and "666–12" means Column Address Strobe (CAS) latency
=6, Row Column Delay (RCD) latency = 6 and Row Precharge (RP) latency = 6 using the JEDEC SPD Revision 1.2 and produced on the
Raw Card "A".
Qimonda
are
1)
1)2)
Module
Organization
64M × 64
available
Description
HYS64T64020EM–[2.5/3/3S/3.7/5]–B2
Compliance Code
512MB 2R×16 PC2–6400M–666–12–A0
512MB 2R×16 PC2–5300M–444–12–A0
512MB 2R×16 PC2–5300M–555–12–A0
512MB 2R×16 PC2–4200M–444–12–A0
512MB 2R×16 PC2–3200M–333–12–A0
as
DRAM Components
HYB18T512160B2F
non-ECC
Memory
Ranks
2
2)
modules
ECC/
Non-ECC
Non-ECC
1)
4
The memory array is designed with 512MBit Double-Data-
Rate-Two (DDR2) Synchronous DRAMs.
capacitors are mounted on the PCB board. The DIMMs
feature serial presence detect based on a serial E
device using the 2-pin I
programmed with configuration data and are write protected;
the second 128 bytes are available to the customer.
Unbuffered DDR2 SDRAM MicroDIMM Modules
8
# of SDRAMs # of row/bank/column
DRAM Density
512Mbit
Description
2 Ranks, Non-ECC
2 Ranks, Non-ECC
2 Ranks, Non-ECC
2 Ranks, Non-ECC
2 Ranks, Non-ECC
HYS64T64020EM–[2.5/3/3S/3.7/5]–B2
bits
13/2/10
2
C protocol. The first 128 bytes are
Components on Modules
DRAM Organisation
32M × 16
Ordering Information
SDRAM Technology
512Mbit (×16)
512Mbit (×16)
512Mbit (×16)
512Mbit (×16)
512Mbit (×16)
Internet Data Sheet
Address Format
TABLE 2
TABLE 3
TABLE 4
Decoupling
Raw
Card
A
2
PROM