m470l6423en0-cb3 Samsung Semiconductor, Inc., m470l6423en0-cb3 Datasheet - Page 10

• Manufacturer Part Number: m470l6423en0-cb3
• Description: 512mb Unbuffered Sodimm Based On Stsop
• Manufacturer: Samsung Semiconductor, Inc.

512MB Unbuffered SODIMM(based on sTSOP)
1. Maximum burst refresh cycle : 8
2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,
4. A write command can be applied with t
5. For registered DIMMs, t
6. Input Setup/Hold Slew Rate Derating
7. I/O Setup/Hold Slew Rate Derating
Mode register set cycle time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
Control & Address input pulse width
DQ & DM input pulse width
Power down exit time
Exit self refresh to non-Read command
Exit self refresh to read command
Refresh interval time
Output DQS valid window
Clock half period
Data hold skew factor
DQS write postamble time
Active to Read with Auto precharge
command
Autoprecharge write recovery +
Precharge time
This derating table is used to increase t
based on the lesser of AC-AC slew rate and DC-DC slew rate.
based on the lesser of AC-AC slew rate and DC-DC slew rate.
This derating table is used to increase t
but system performance (bus turnaround) will degrade accordingly.
jitter due to crosstalk (t
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on tDQSS.
Input Setup/Hold Slew Rate
I/O Setup/Hold Slew Rate
Parameter
(V/ns)
(V/ns)
0.5
0.4
0.3
0.5
0.4
0.3
JIT
CL
(crosstalk)
and t
CH
are t 45% of the period including both the half period jitter (t
) on the DIMM.
RCD
DS
IS
/t
Symbol
/t
tXSNR
tXSRD
tWPST
+100
IH
'tDS
+150
tDIPW
tPDEX
DH
'tIS
tMRD
tREFI
tQHS
(ps)
+50
(ps)
+75
tRAP
tIPW
tDAL
satisfied after this command.
tQH
tDS
tDH
tHP
0
0
in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate
in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate
(tWR/tCK)
or tCHmin
(tRP/tCK)
tCLmin
-tQHS
0.45
0.45
1.75
Min
200
tHP
2.2
0.4
12
75
18
6
+
'tDH
+100
+150
B3
'tIH
(ps)
+50
(ps)
+75
0
0
Max
0.55
7.8
0.6
-
-
or tCHmin
(tWR/tCK)
(tRP/tCK)
tCLmin
-tQHS
Min
1.75
200
tHP
0.5
7.5
0.5
2.2
0.4
15
75
20
+
A2
Max
0.75
7.8
0.6
-
-
JIT(HP)
(tWR/tCK)
or tCHmin
(tRP/tCK)
tCLmin
-tQHS
Rev. 1.3 March. 2004
1.75
Min
200
tHP
0.5
0.5
2.2
7.5
0.4
15
75
20
+
) of the PLL and the half period
B0
DDR SDRAM
Max
0.75
7.8
0.6
-
-
Unit
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
Note
7,8,9
7,8,9
11
4
1
5
3