mt9htf12872az Micron Semiconductor Products, mt9htf12872az Datasheet - Page 9

• Manufacturer Part Number: mt9htf12872az
• Description: 1gb X72, Sr, Ecc 240-pin Ddr2 Sdram Udimm
• Manufacturer: Micron Semiconductor Products

I
Table 8:
PDF: 09005aef83b961d6/Source: 09005aef83b96204
HTF9C128x72AZ.fm - Rev. A 7/09 EN
Parameter/Condition
Operating one bank active-precharge current:
t
Address bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
CL = CL (I
t
Address bus inputs are switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
Other control and address bus inputs are stable; Data bus inputs are floating
Precharge quiet standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs
are floating
Precharge standby current: All device banks idle;
HIGH; Other control and address bus inputs are switching; Data bus inputs are
switching
Active power-down current: All device banks open;
t
bus inputs are stable; Data bus inputs are floating
Active standby current: All device banks open;
t
commands; Other control and address bus inputs are switching; Data bus inputs
are switching
Operating burst write current: All device banks open; Continuous burst writes;
BL = 4, CL = CL (I
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching;
Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst reads;
I
t
are switching; Data bus inputs are switching
Burst refresh current:
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤0.2V; Other control and address bus
inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving reads;
I
t
valid commands; Address bus inputs are stable during deselects; Data bus inputs are
switching
DD
OUT
OUT
RAS =
RCD =
CK =
RAS =
RP =
RC =
Specifications
= 0mA; BL = 4, CL = CL (I
= 0mA; BL = 4, CL = CL (I
t
t
t
RP (I
RC (I
CK (I
t
t
t
RAS MIN (I
RAS MAX (I
RCD (I
DD
DD
DD
DD
), AL = 0;
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
),
DDR2 I
Values shown for MT47H32M8 DDR2 SDRAM only and are computed from values specified in the
1Gb (128 Meg x 8) component data sheet
); CKE is LOW; Other control and address
DD
t
RRD =
DD
); CKE is HIGH, S# is HIGH between valid commands;
DD
), AL = 0;
DD
); CKE is HIGH, S# is HIGH between valid commands;
t
),
CK =
DD
t
RRD (I
t
RP =
t
CK =
Specifications and Conditions – 1GB
t
CK (I
t
DD
DD
CK =
DD
t
RP (I
t
CK (I
), AL = 0;
), AL =
),
DD
t
RCD =
t
DD
),
CK (I
DD
t
); CKE is HIGH, S# is HIGH between valid
RC =
); REFRESH command at every
t
RCD (I
DD
t
t
RCD (I
CK =
),
t
RC (I
t
RAS =
DD
t
CK (I
DD
) - 1 x
DD
t
); CKE is HIGH, S# is HIGH between
),
CK =
t
t
t
RAS MAX (I
t
DD
CK =
CK =
RAS =
t
CK (I
),
1GB (x72, SR, ECC) 240-Pin DDR2 SDRAM UDIMM
t
CK (I
t
t
RAS =
t
t
CK =
OUT
CK (I
CK (I
DD4W
t
t
DD
CK =
RAS MIN (I
9
DD
);
= 0mA; BL = 4,
DD
t
DD
DD
CK (I
),
t
t
CK =
RAS MAX (I
t
),
); CKE is HIGH, S# is
CK (I
),
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
t
t
RC =
DD
RP =
t
RFC (I
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
CK (I
); CKE is LOW;
DD
); CKE is
t
),
t
RC (I
RP (I
DD
DD
DD
),
)
DD
),
DD
),
);
Symbol
I
I
I
I
I
I
I
I
DD3PF
DD3PS
DD4W
DD2Q
I
I
DD2N
DD3N
I
I
I
Electrical Specifications
DD2P
DD4R
DD0
DD1
DD5
DD6
DD7
©2003 Micron Technology, Inc. All rights reserved.
-80E/
1440
1440
2115
3015
-800
810
990
450
450
360
540
63
90
63
1215
1215
1935
2520
-667
765
900
360
360
270
495
63
90
63
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA