mt9htf12872pky-53e Micron Semiconductor Products, mt9htf12872pky-53e Datasheet - Page 9

• Manufacturer Part Number: mt9htf12872pky-53e
• Description: 256mb, 512mb, 1gb X72, Sr 244-pin Ddr2 Registered Minidimm
• Manufacturer: Micron Semiconductor Products

Table 9:
PDF: 09005aef817ab1fc/Source: 09005aef817ab1dd
HTF9C32_64_128x72K.fm - Rev. C 9/06 EN
Parameter/Condition
Operating one bank active-precharge current;
(I
Address bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current; I
CL (I
t
are switching; Data pattern is same as I
Precharge power-down current; All device banks idle;
LOW; Other control and address bus inputs are stable; Data bus inputs are
floating
Precharge quiet standby current; All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are STABLE; Data bus
inputs are floating
Precharge standby current; All device banks idle;
S# is HIGH; Other control and address bus inputs are switching; Data bus inputs
are switching
Active power-down current; All device banks open;
(I
stable; Data bus inputs are floating
Active standby current; All device banks open;
MAX (I
Other control and address bus inputs are switching; Data bus inputs are
switching
Operating burst write current; All device banks open, continuous burst
writes; BL = 4, CL = CL (I
t
are switching; Data bus inputs are switching
Operating burst read current; All device banks open, continuous burst reads,
I
t
inputs are switching; Data bus inputs are switching
Burst refresh current;
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
Self refresh current; CK and CK# at 0V; CKE ≤ 0.2V; Other control and address
bus inputs are FLOATING; Data bus inputs are floating
Operating bank interleave read current; All device banks interleaving reads,
I
=
valid commands; Address bus inputs are stable during deselects; Data bus inputs
are switching; See I
RCD (I
RP (I
OUT
RP =
OUT
DD
DD
t
RC (I
),
); CKE is LOW; Other control and address bus inputs are
= 0mA; BL = 4, CL = CL (I
DD
= 0mA; BL = 4, CL = CL (I
DD
t
t
RAS =
RP (I
), AL = 0;
DD
DD
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
),
),
DD
t
t
RRD =
RP =
t
); CKE is HIGH, S# is HIGH between valid commands; Address bus
RAS MIN (I
I
Values shown for DDR2 SDRAM components only
DD
t
CK =
t
RP (I
Specifications and Conditions – 256MB
t
RRD (I
DD
7 Conditions for detail
DD
t
CK (I
DD
DD
t
); CKE is HIGH, S# is HIGH between valid commands;
CK =
DD
), AL = 0;
); CKE is HIGH, S# is HIGH between valid commands;
DD
DD
),
DD
t
256MB, 512MB, 1GB: (x72, SR) 244-Pin DDR2 Registered MiniDIMM
),
t
), AL =
RCD =
CK (I
), AL = 0;
t
RC =
t
DD
CK =
t
t
RCD (I
t
RCD (I
); REFRESH command at every
RC (I
DD
t
t
CK =
4W
CK (I
DD
DD
DD
),
); CKE is HIGH, S# is HIGH between
) -1 ×
t
DD
t
CK (I
RAS =
),
t
CK =
t
t
t
RAS =
t
DD
CK =
CK (I
CK =
t
),
t
RAS MIN (I
CK =
t
CK (I
t
DD
RAS =
OUT
t
t
CK (I
t
CK =
t
t
CK (I
RAS MAX (I
CK =
);
t
9
DD
= 0mA; BL = 4, CL =
t
CK
CK =
DD
DD
t
),
t
CK (I
RAS MAX (I
t
CK (I
),
t
DD
); CKE is HIGH,
RAS =
Fast PDN Exit
MR[12] = 0
Slow PDN Exit
MR[12] = 1
t
t
RC =
CK (I
),
t
DD
RFC (I
DD
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
RCD =
); CKE is
); CKE is
t
DD
t
),
RAS
RC
DD
t
),
RP =
DD
t
)
RC
),
Symbol
I
I
I
I
I
I
I
DD
DD
DD
DD
DD
I
I
DD
DD
I
I
I
DD
DD
DD
DD
DD
4W
2Q
2N
3N
4R
2P
3P
0
1
5
6
7
Electrical Specifications
1,710
1,620
1,620
2250
-667
810
900
360
360
270
450
45
54
45
©2005 Micron Technology, Inc. All rights reserved.
1,440
1,350
1,530
2,160
-53E
720
810
315
315
225
360
45
54
45
1,125
1,035
1,485
2,070
-40E
675
765
225
270
180
270
45
54
45
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA