mt9htf12872pky-53e Micron Semiconductor Products, mt9htf12872pky-53e Datasheet - Page 4

• Manufacturer Part Number: mt9htf12872pky-53e
• Description: 256mb, 512mb, 1gb X72, Sr 244-pin Ddr2 Registered Minidimm
• Manufacturer: Micron Semiconductor Products

Table 7:
PDF: 09005aef817ab1fc/Source: 09005aef817ab1dd
HTF9C32_64_128x72K.fm - Rev. C 9/06 EN
RAS#, CAS#, WE#
RDQS0#–RDQS8#
(256MB,
(512MB, 1GB)
DQS0–DQS8,
DQ0–DQ63
DM0–DM8
CK0, CK0#
BA0, BA1
BA0–BA2
SA0–SA2
CB0–CB7
Symbol
(256MB)
A0–A12
A0–A13
RESET#
P
ODT0
(1GB)
CKE0
AR
S0#
SCL
_I
512MB)
N
Pin Descriptions
Input On-Die termination: ODT (registered HIGH) enables termination resistance internal to the
Input Clock: CK and CK# are differential clock inputs. All address and control input signals are
Input Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking
Input Chip select: S# enables (registered LOW) and disables (registered HIGH) the command decoder.
Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered.
Input Bank address inputs: BA0–BA1/BA2 define to which device bank an ACTIVE, READ, WRITE, or
Input Address inputs: Provide the row address for ACTIVE commands, and the column address and
Input Parity bit for the address and control bus.
Input Serial clock for presence-detect: SCL is used to synchronize the presence-detect data transfer
Input Presence-Detect address inputs: These pins are used to configure the presence-detect
Input Asynchronously forces all registered outputs LOW when RESET# is LOW. This signal can be used
Type
I/O
I/O
I/O
I/O
DDR2 SDRAM. When enabled, ODT is only applied to each of the following pins: DQ, DQS,
DQS#, RDQS, RDQS#, CB, and DM. The ODT input will be ignored if disabled via the LOAD
MODE (LM) command.
sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data
(DQs and DQS/DQS#) is referenced to the crossings of CK and CK#.
circuitry on the DDR2 SDRAM. The specific circuitry that is enabled/disabled is dependent on the
DDR2 SDRAM configuration and operating mode. CKE LOW provides PRECHARGE power-down
and SELF REFRESH operations (all device banks idle), or ACTIVE power-down (row ACTIVE in any
device bank). CKE is synchronous for power-down entry, power-down exit, output disable, and
for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit. Input buffers (excluding CK,
CK#, CKE, and ODT) are disabled during power-down. Input buffers (excluding CKE) are
disabled during SELF REFRESH. CKE is an SSTL_18 input but will detect a LVCMOS LOW level
once V
and initialization sequence, it must be maintained for proper operation of the CKE receiver. For
proper SELF-REFRESH operation V
All commands are masked when S# is registered HIGH. S# provides for external rank selection
on systems with multiple ranks. S# is considered part of the command code.
PRECHARGE command is being applied. BA0–BA1/BA2 define which mode register including
MR, EMR, EMR(2), and EMR(3) is loaded during the LM command.
auto precharge bit (A10) for Read/WRITE commands, to select one location out of the memory
array in the respective bank. A10 sampled during a PRECHARGE command determines whether
the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0–BA1/BA2)
or all device banks (A10 HIGH). The address inputs also provide the op-code during a LM
command.
to and from the module.
device.
during power up to ensure that CKE is LOW and DQs are High-Z.
Data Input/output: Bidirectional data bus.
Data strobe: Output with read data, input with write data for source synchronous operation.
Edge-aligned with read data, center aligned with write data. DQS# is only used when
differential data strobe mode is enabled via the LM command. DQS9#–DQS17# are only used
when RDQS# is enabled via the LM command.
Input data mask: DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges
of DQS. Although DM pins are input-only, the DM loading is designed to match that of DQ and
DQS pins. If RDQS is enabled, DQS9#–DQS17# are used only during the READ command. If RDQS
is disabled, DQS0–DQS17 become DM0–DM8 and DQS9#–DQS17# are not used.
Check bits.
256MB, 512MB, 1GB: (x72, SR) 244-Pin DDR2 Registered MiniDIMM
DD
is applied during first power-up. After Vref has become stable during the power on
4
REF
must be maintained to this input.
Description
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Pin Assignments and Descriptions
©2005 Micron Technology, Inc. All rights reserved.