k4s64323lh Samsung Semiconductor, Inc., k4s64323lh Datasheet

k4s64323lh

Manufacturer Part Number

k4s64323lh

Description

512k X 32bit X 4 Banks Mobile Sdram In 90fbga

Manufacturer

Samsung Semiconductor, Inc.

Datasheet

1.K4S64323LH.pdf (12 pages)

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Company:

Bonase Electronics (HK) Co., Limited

Part Number:

k4s64323lh-HN75

Manufacturer:

SAMSUNG

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K4S64323LH - F(H)E/N/G/C/L/F

512K x 32Bit x 4 Banks Mobile SDRAM in 90FBGA

FEATURES

• 2.5V power supply.

• LVCMOS compatible with multiplexed address.

• Four banks operation.

• MRS cycle with address key programs.

• EMRS cycle with address key programs.

• All inputs are sampled at the positive going edge of the system

• Burst read single-bit write operation.

• Special Function Support.

• DQM for masking.

• Auto refresh.

• 64ms refresh period (4K cycle).

• Commercial Temperature Operation (-25qC ~ 70qC).

• Extended Temperature Operation (-25qC ~ 85qC).

• 90Balls FBGA with 0.8mm ball pitch

ORDERING INFORMATION

- F(H)E/N/G : Normal/Low/Low Power, Extended Temperature(-25qC ~ 85qC)

- F(H)C/L/F : Normal/Low/Low Power, Commercial Temperature(-25qC ~ 70qC)

NOTES :

1. In case of 40MHz Frequency, CL1 can be supported.

2. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake.

( -FXXX : Leaded, -HXXX : Lead Free).

Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific

purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.

clock.

-. CAS latency (1, 2 & 3).

-. Burst length (1, 2, 4, 8 & Full page).

-. Burst type (Sequential & Interleave).

-. PASR (Partial Array Self Refresh).

-. Internal TCSR (Temperature Compensated Self Refresh)

K4S64323LH-F(H)E/N/G/C/L/F1H

K4S64323LH-F(H)E/N/G/C/L/F60

K4S64323LH-F(H)E/N/G/C/L/F75

K4S64323LH-F(H)E/N/G/C/L/F1L

Part No.

105MHz(CL=3)

166MHz(CL=3)

133MHz(CL=3)

105MHz(CL=2)

Max Freq.

GENERAL DESCRIPTION

rate Dynamic RAM organized as 4 x 524,288 words by 32 bits,

fabricated with SAMSUNG’s high performance CMOS technol-

ogy. Synchronous design allows precise cycle control with the

use of system clock and I/O transactions are possible on every

clock cycle. Range of operating frequencies, programmable

burst lengths and programmable latencies allow the same

device to be useful for a variety of high bandwidth and high per-

formance memory system applications.

The K4S64323LH is 67,108,864 bits synchronous high data

Interface

LVCMOS

Mobile-SDRAM

Leaded (Lead Free)

Package

90 FBGA

February 2004

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