k4s64323lf-dg15 Samsung Semiconductor, Inc., k4s64323lf-dg15 Datasheet - Page 7

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k4s64323lf-dg15

Manufacturer Part Number
k4s64323lf-dg15
Description
2mx32 Mobile Sdram 90fbga
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
K4S64323LF-S(D)G/S
AC CHARACTERISTICS
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
CLK cycle time
CLK to valid output delay
Output data hold time
CLK high pulse width
CLK low pulse width
Input setup time
Input hold time
CLK to output in Low-Z
CLK to output in Hi-Z
Note :
1. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
a product contained herein for any specific purpose, such as medical, aerospace, nuclear, military, vehicular or undersea
repeater use.
is potentially at stake. Please contact to the memory marketing team in samsung electronics when considering the use of
Parameter
CAS latency=3
CAS latency=2
CAS latency=1
CAS latency=3
CAS latency=2
CAS latency=1
CAS latency=3
CAS latency=2
CAS latency=1
CAS latency=3
CAS latency=2
CAS latency=1
(AC operating conditions unless otherwise noted)
Symbol
t
t
t
t
t
t
t
SAC
t
t
SHZ
SLZ
C C
O H
C H
CL
SS
SH
Min
7.5
9.5
2.5
2.5
2.5
2.5
2.0
1.0
1
-
-
- 75
1000
Max
5.4
5.4
7
7
-
-
Min
9.5
9.5
2.5
2.5
2.5
1.5
3
3
1
-
-
-1H
1000
Max
7
7
7
7
-
-
Min
9.5
2.5
2.5
2.5
2.5
1.5
12
25
3
3
1
-1L
1000
Max
20
20
7
8
7
8
Min
2.5
2.5
2.5
3.5
3.5
3.5
2.0
15
15
30
1
CMOS SDRAM
Rev. 1.5 Dec 2002
- 15
1000
Max
24
24
9
9
9
9
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
1,2
1
2
3
3
3
3
2

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