k4h560838c Samsung Semiconductor, Inc., k4h560838c Datasheet - Page 20

• Manufacturer Part Number: k4h560838c
• Description: Ddr Sdram Specification Version 0.6
• Manufacturer: Samsung Semiconductor, Inc.

256Mb C-die(x4/8) DDR SDRAM
The essential functionality that is required for the DDR SDRAM device is described in this chapter
command is issued by asserting CS and CAS low while holding RAS and WE high at the rising edge of the
clock(CK) after tRCD from the bank activation. The address inputs (A0~A9) determine the starting address for
the Burst. The Mode Register sets type of burst(Sequential or interleave) and burst length(2, 4, 8). The first
output data is available after the CAS Latency from the READ command, and the consecutive data are pre-
sented on the falling and rising edge of Data Strobe(DQS) adopted by DDR SDRAM until the burst length is
completed.
3.3 Essential Functionality for DDR SDRAM
3.3.1 Burst Read Operation
CAS Latency=2
CAS Latency=2.5
Burst Read operation in DDR SDRAM is in the same manner as the current SDRAM such that the Burst read
< Burst Length=4, CAS Latency= 2, 2.5 >
Command
CK
CK
DQS
D Q s
DQS
D Q s
READ A
0
NOP
Figure 9. Burst read operation timing
1
t
RPRE
NOP
Dout 0 Dout 1 Dout 2 Dout 3
2
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Dout 0 Dout 1 Dout 2 Dout 3
NOP
3
t
RPST
NOP
4
NOP
5
REV. 0.7 Jan. 31. 2002
NOP
6
NOP
7
NOP
8