k4s160822d Samsung Semiconductor, Inc., k4s160822d Datasheet - Page 7

• Manufacturer Part Number: k4s160822d
• Description: 2mx8 Sdram 1m X 8bit X 2 Banks Synchronous Dram Lvttl
• Manufacturer: Samsung Semiconductor, Inc.

K4S160822D
AC OPERATING TEST CONDITIONS
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Notes :
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to new col. address delay
Last data in to burst stop
Col. address to col. address delay
Number of valid output data
Output
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
(Fig. 1) DC output load circuit
and then rounding off to the next higher integer.
870
Parameter
Parameter
3.3V
1200
50pF
CAS latency=3
CAS latency=2
V
V
OH
OL
t
t
t
t
t
t
t
t
RAS
RRD
RCD
t
t
CCD
(DC) = 0.4V, I
Symbol
RAS
RDL
CDL
BDL
(DC) = 2.4V, I
RP
RC
(V
(min)
(min)
(max)
DD
(min)
(min)
(min)
(min)
(min)
(min)
(min)
= 3.3V 0.3V, T
- 7 -
OH
OL
14
20
20
48
68
-7
7
= -2mA
= 2mA
A
16
20
20
48
68
-8
8
= 0 to 70 C)
See Fig. 2
tr/tf = 1/1
2.4/0.4
Value
1.4
1.4
Output
Version
20
20
20
50
100
70
10
-H
1
1
1
2
1
(Fig. 2) AC output load circuit
20
20
20
50
70
10
-L
Z0 = 50
-10
20
26
26
50
80
12
CMOS SDRAM
Rev. 1.0 (Oct. 1999)
Unit
CLK
CLK
CLK
ns
ns
ns
ns
us
ns
ns
ea
Vtt = 1.4V
Unit
50
ns
50pF
V
V
V
Note
1
1
1
1
1
2
2
2
3
4