k4t1g084qc Samsung Semiconductor, Inc., k4t1g084qc Datasheet - Page 26

• Manufacturer Part Number: k4t1g084qc
• Description: 1gb C-die Ddr2 Sdram Specification
• Manufacturer: Samsung Semiconductor, Inc.

29. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the V
30. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the V
31. Input waveform timing is referenced from the input signal crossing at the V
32. Input waverorm timing is referenced from the input signal crossing at the V
33. tWTR is at lease two clocks (2 * tCK) independent of operation frequency.
34. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(ac) level to the
35. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the VIH(dc) level to the
36. tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire
K4T1G044QC
K4T1G084QC
differential data strobe crosspoint for a rising signal, and from the input signal crossing at the V
a falling signal applied to the device under test.
differential data strobe crosspoint for a rising signal and V
test.
device under test.
device under test.
single-ended data strobe crossing VIH/L(dc) at the start of its transition for a rising signal, and from the input signal crossing at the VIL(ac) level to the
single-ended data strobe crossing VIH/L(dc) at the start of its transition for a falling signal applied to the device under test. The DQS signal must be
monotonic between Vil(dc)max and Vih(dc)min.
single-ended data strobe crossing VIH/L(ac) at the end of its transition for a rising signal, and from the input signal crossing at the VIL(dc) level to the
single-ended data strobe crossing VIH/L(ac) at the end of its transition for a falling signal applied to the device under test. The DQS signal must be
monotonic between Vil(dc)max and Vih(dc)min.
time it takes to achieve the 3 clocks of registeration. Thus, after any CKE transition, CKE may not change from its valid level during the time period of
tIS + 2*tCK + tIH.
CK
CK
DQS
DQS
tIS
< Differential Input waveform timing >
tDS
IL(dc)
tIH
tDH
to the differential data strobe crosspoint for a falling signal applied to the device under
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IH(ac)
IL(dc)
tIS
tDS
) level for a rising signal and V
level for a rising signal and V
tIH
tDH
IL(ac)
level to the differential data strobe crosspoint for
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DDQ
IH(ac)
IH(dc)
REF(dc)
IL(dc)
IL(ac)
SS
IL(ac)
DDQ
IH(ac)
IH(dc)
REF(dc)
IL(dc)
IL(ac)
SS
IH
(dc) for a falling signal applied to the
for a falling signal applied to the
max
max
max
max
min
min
min
min
DDR2 SDRAM
Rev. 1.1 June 2007
IH(ac)
IH(dc)
level to the
level to the