m36l0t7050t2 Numonyx, m36l0t7050t2 Datasheet - Page 10

• Manufacturer Part Number: m36l0t7050t2
• Description: 128 Mbit Multiple Bank, Multi-level, Burst Flash Memory And 32 Mbit 2mb X16 Psram, Multi-chip Package
• Manufacturer: Numonyx

Signal descriptions
2.6
2.7
2.8
2.9
2.10
2.11
10/22
Flash Write Protect (WP
Write Protect is an input that gives an additional hardware protection for each block. When
Write Protect is Low, V
Down blocks cannot be changed. When Write Protect is at High, V
and the Locked-Down blocks can be locked or unlocked. (See the Lock Status Table in the
M58LT128HTB datasheet).
Flash Reset (RP
The Reset input provides a hardware reset of the memory. When Reset is at V
memory is in Reset mode: the outputs are high impedance and the current consumption is
reduced to the Reset Supply Current I
of I
reset. When Reset is at V
device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch
Enable is required to ensure valid data outputs.
The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied
to V
Flash Latch Enable (L
Latch Enable latches the address bits on its rising edge. The address latch is transparent
when Latch Enable is Low, V
Enable can be kept Low (also at board level) when the Latch Enable function is not required
or supported.
Flash Clock (K
The Clock input synchronizes the Flash memory to the microcontroller during synchronous
read operations; the address is latched on a Clock edge (rising or falling, according to the
configuration settings) when Latch Enable is at V
Read and in write operations.
Flash Wait (WAIT
WAIT is a Flash output signal used during Synchronous Read to indicate whether the data
on the output bus are valid. This output is high impedance when Flash Chip Enable is at V
or Flash Reset is at V
cycle in advance. The WAIT
PSRAM Chip Enable Input (E1
When asserted (Low), the Chip Enable, E1
buffers and decoders, allowing Read and Write operations to be performed. When de-
asserted (High), all other pins are ignored, and the device is put, automatically, in low-power
Standby mode.
It is not allowed to set E
DD2
RPH
. After Reset all blocks are in the Locked state and the Configuration Register is
(refer to M58LT128HTB datasheet).
IL
F
IL
. It can be configured to be active during the wait cycle or one clock
)
F
F
, Lock-Down is enabled and the protection status of the Locked-
at V
F
)
IH
)
, the device is in normal operation. Exiting Reset mode the
F
IL
IL,
signal is not gated by Output Enable.
, and it is inhibited when Latch Enable is High, V
E1
F
)
P
F
at V
)
DD2
IL
. Refer to M58LT128HTB datasheet for the value
P
and E2
, activates the memory state machine, address
P
)
IL
. Clock is don't care during Asynchronous
P
at V
IH
M36L0T7050T2, M36L0T7050B2
at the same time.
IH
, Lock-Down is disabled
IL
IH
, the
. Latch
IH