m36l0r7060u1 STMicroelectronics, m36l0r7060u1 Datasheet - Page 12

• Manufacturer Part Number: m36l0r7060u1
• Description: 128 Mbit Mux I/o, Multiple Bank, Multi-level, Burst Flash Memory, 32 Or 64 Mbit Psram, 1.8v Supply Multi-chip Package
• Manufacturer: STMicroelectronics

Signal descriptions
2.12
2.13
2.14
2.15
2.16
2.17
2.18
12/22
PSRAM Output Enable (G
When held Low, V
memory.
PSRAM Write Enable (W
Write Enable, W
device is in write mode and write operations can be performed either to the configuration
registers or to the memory array.
PSRAM Upper Byte Enable (UB
The Upper Byte Enable, UB
Inputs/Outputs (ADQ8-ADQ15) to or from the upper part of the selected address during a
write or read operation.
PSRAM Lower Byte Enable (LB
The Lower Byte Enable, LB
Input/Outputs (ADQ0-ADQ7) to or from the lower part of the selected address during a write
or read operation.
If both LB
or transmitting data. Although the device will seem to be deselected, it remains in an active
mode as long as E
PSRAM Configuration Register Enable (CR
When this signal is driven High, V
the Refresh Configuration Register (RCR) or the Bus Configuration Register (BCR)
according to the value of A19.
V
V
power supply for all Flash memory operations (Read, Program and Erase).
V
The V
DDF
DDF
CCP
provides the power supply to the internal core of the Flash memory. It is the main
CCP
Flash memory Supply Voltage
PSRAM Supply Voltage
P
Supply Voltage is the core supply voltage.
and UB
P
, controls the Bus Write operation of the memory. When asserted (V
IL
P
P
, the Output Enable, G
remains Low.
are disabled (High), the device will disable the data bus from receiving
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
P
P
, gates the data on the Lower Byte of the Address Inputs/Data
, gates the data on the Upper Byte of the Address Inputs/ Data
IH
, bus read or write operations access either the value of
P
)
P
)
P
, enables the Bus Read operations of the
P
P
)
)
P
)
IL
), the