m36l0r7060u1 STMicroelectronics, m36l0r7060u1 Datasheet - Page 11

• Manufacturer Part Number: m36l0r7060u1
• Description: 128 Mbit Mux I/o, Multiple Bank, Multi-level, Burst Flash Memory, 32 Or 64 Mbit Psram, 1.8v Supply Multi-chip Package
• Manufacturer: STMicroelectronics

M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
2.6
2.7
2.8
2.9
2.10
2.11
Flash memory Chip Enable (E
The Chip Enable input activates the memory control logic, input buffers, decoders and
sense amplifiers. When Chip Enable is at V
mode. When Chip Enable is at V
impedance and the power consumption is reduced to the stand-by level.
It is not allowed to set both E
Flash memory Output Enable (G
The Output Enable input controls data outputs during the Bus Read operation of the Flash
memory.
Flash memory Write Enable (W
The Write Enable input controls the Bus Write operation of the Flash memory’s Command
Interface. The data and address inputs are latched on the rising edge of Chip Enable or
Write Enable whichever occurs first.
Flash memory Write Protect (WP
Write Protect is an input that gives an additional hardware protection for each block. When
Write Protect is at V
Down blocks cannot be changed. When Write Protect is at V
and the Locked-Down blocks can be locked or unlocked. (refer to M58LRxxxGUL
datasheet).
Flash memory Reset (RP
The Reset input provides a hardware reset of the memory. When Reset is at V
memory is in reset mode: the outputs are high impedance and the current consumption is
reduced to the Reset Supply Current I
value of I
reset. When Reset is at V
enters asynchronous read mode, but a negative transition of Chip Enable or Latch Enable is
required to ensure valid data outputs.
The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied
to V
PSRAM Chip Enable (E
Chip Enable, E
the device is disabled and goes automatically in low-power Standby mode or Deep Power-
Down mode, according to the RCR settings.
It is not allowed to set both E
RPH
(refer to the M58LRxxxGUL datasheet).
DD2.
After Reset all blocks are in the Locked state and the Configuration Register is
P
, activates the device when driven Low (asserted). When de-asserted (V
IL
, the Lock-Down is enabled and the protection status of the Locked-
IH
, the device is in normal operation. Exiting reset mode the device
F
F
and E
and E
IH
P
the memory is deselected, the outputs are high
)
P
P
F
DD2
to V
to V
)
. Refer to the M58LRxxxGUL datasheet for the
IL
IL
IL
at the same time.
at the same time.
F
and Reset is at V
)
F
)
F
F
)
)
IH
IH
, the Lock-Down is disabled
the device is in active
Signal descriptions
IL
, the
11/22
IH
),