am41lv3204m Meet Spansion Inc., am41lv3204m Datasheet
am41lv3204m
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am41lv3204m Summary of contents
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... Am41LV3204M Data Sheet July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, these products will be offered to customers of both AMD and Fujitsu ...
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... PRELIMINARY Am41LV3204M Stacked Multi-chip Package (MCP) 32 Mbit ( bit 16-bit) Flash Memory and 4 Mbit (512K x 8-Bit/256 K x 16-Bit) Static RAM DISTINCTIVE CHARACTERISTICS MCP Features Power supply voltage of 2.7 to 3.3 volt High Performance — Access time as fast as 100ns initial 30 ns page Flash ...
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... AMD MirrorBit flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effec- tiveness. The device electrically erases all bits within a sector simultaneously via hot-hole assisted erase. The data is programmed using hot electron injection. Am41LV3204M June 10, 2003 ...
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... Erase And Programming Performance Flash Latchup Characteristics Package Pin Capacitance Data Retention SRAM Data Retention . . . . . . . . . . . . . . . . . . . . . . 62 Figure 31. CE#1 Controlled Data Retention Mode......................... 62 Figure 32. CE2s Controlled Data Retention Mode......................... 62 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 63 TLB069—69-Ball Fine-pitch Ball Grid Array (FBGA Package ................................................................ 64 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 65 Am41LV3204M 3 ...
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... CE1#s CE2s CIOs Am41LV3204M Flash Memory 10 100 100 RY/BY Bit Flash Memory DQ15/A-1 to DQ0 V s CCQ SS SSQ 4 M Bit DQ15/A-1 to DQ0 Static RAM Am41LV3204M SRAM N/A 35 DQ15/A-1 to DQ0 June 10, 2003 ...
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... Register CE#f OE# V Detector CC A20–A0 June 10, 2003 Sector Switches Erase Voltage Generator PGM Voltage Generator Chip Enable Output Enable Logic Y-Decoder STB Timer X-Decoder Am41LV3204M – DQ15 DQ0 Input/Output Buffers Data STB Latch Y-Gating Cell Matrix 5 ...
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... V s DQ12 DQ7 DQ11 CIOs DQ5 DQ14 integrity may be compromised if the package body is exposed to temperatures about 150 C for prolonged periods of time. Am41LV3204M Flash only A10 NC SRAM only Shared C9 A15 E10 F10 A16 ...
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... Highest Order Address Pin (SRAM) Byte Mode CIOf = I/O Configuration (Flash) CIOf = V = Word Mode (x16) IH CIOf = V = Byte Mode (X8) IL June 10, 2003 LOGIC SYMBOL 21 A20–A0 CE1#s CE2s OE# WE# WP#/ACC RESET#f UB#s LB#s CIOs SA# CIOf Am41LV3204M DQ15–DQ0 (A-1) RY/BY# 7 ...
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... SRAM DEVICE DENSITY Mbits Valid Combinations list configurations planned to be supported in vol- Package Marking ume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly re- M410000095 leased combinations M410000096 Am41LV3204M Valid Combinations June 10, 2003 ...
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... The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the in- puts and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Am41LV3204M 9 ...
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... Don’t Care SRAM Address Address In Data In and CE2s = V at the same time the boot sectors protection will be removed. IH Am41LV3204M , SRAM Word Mode, CIOs = WP#/ACC DQ7– DQ15– (Note 4) DQ0 X H L/H D OUT ...
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... Don’t Care SRAM Address Address In Data In and CE2s = V at the same time the boot sectors protection will be removed. IH Am41LV3204M , SRAM Word Mode, CIOs = V IH UB#s WP#/ACC DQ7– RESET# (Note 3) (Note 4) DQ0 X H L/H D OUT ...
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... Don’t Care SRAM Address Address In (for Flash Byte Mode, DQ15 = A-1 and CE2s = V at the same time the boot sectors protection will be removed. IH Am41LV3204M ; SRAM Word Mode, CIOs = V IL UB#s WP#/ACC DQ7– RESET# (Note 3) (Note 4) DQ0 X H ...
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... Don’t Care SRAM Address Address In (for Flash Byte Mode, DQ15 = A-1 and CE2s = V at the same time the boot sectors protection will be removed. IH Am41LV3204M ; SRAM Byte Mode, CIOs = UB#s WP#/ACC DQ7– RESET# (Note 3) (Note 4) DQ0 X ...
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... In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE#f and RESET# pins are both held at V Am41LV3204M 3 and 2 indicates the AC Char- ...
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... Refer to the AC Characteristics rameters and to Figure 16 for the timing diagram. Output Disable Mode When the OE# input disabled. The output pins are placed in the high impedance state. Am41LV3204M , the RP ±0.3 V, the device RESET# is held CC4 ±0.3 V, the standby current will ...
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... Am41LV3204M (x16) Address Range 00000h–07FFFh 08000h–0FFFFh 10000h–17FFFh 18000h–1FFFFh 20000h–27FFFh 28000h–2FFFFh 30000h–37FFFh 38000h–3FFFFh 40000h–47FFFh 48000h–4FFFFh 50000h–57FFFh 58000h–5FFFFh 60000h– ...
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... Am41LV3204M (x16) Address Range 1A8000h–1AFFFFh 1B0000h–1B7FFFh 1B8000h–1BFFFFh 1C0000h–1C7FFFh 1C8000h–1CFFFFh 1D0000h–1D7FFFh 1D8000h–1DFFFFh 1E0000h–1E7FFFh 1E8000h–1EFFFFh 1F0000h–1F7FFFh 1F8000h–1F8FFFh 1F9000h–1F9FFFh 1FA000h– ...
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... Kbytes or last sector independently of whether those sectors were protected or unprotected using the method de- 8 Kbytes scribed in “Sector Group Protection and Unprotection”. 8 Kbytes Note that if WP#/ACC Kbytes Am41LV3204M Sector/ A20–A12 Sector Block Size 111111011h 8 Kbytes 111111100h 8 Kbytes ...
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... Notes: 1. All protected sector groups unprotected (If WP the first or last sector will remain protected). 2. All previously protected sector groups are protected once again. Figure 1. Temporary Sector Group Unprotect Operation Am41LV3204M START RESET (Note 1) Perform Erase or Program Operations RESET ...
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... Reset PLSCNT = 1 Increment PLSCNT No Yes PLSCNT = 1000? Yes Device failed Sector Group Unprotect Algorithm Am41LV3204M START PLSCNT = 1 RESET Wait 1 s Temporary Sector No First Write Group Unprotect Cycle = 60h? Mode Yes All sector No groups ...
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... To verify the protect/unprotect status of the SecSi Sector, follow the algorithm shown in Figure 3. Once the SecSi Sector is programmed, locked and verified, the system must write the Exit SecSi Sector Region command sequence to return to reading and writing within the remainder of the array. Am41LV3204M Table 5 for Command Definitions ...
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... For further information, please refer to the CFI Specifi- cation and CFI Publication 100, available via the World Wide Web at http://www.amd.com/flash/cfi. Al- ternatively, contact an AMD representative for copies of these documents. Am41LV3204M , the device does not ac- LKO is greater than V CC LKO ...
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... Typical timeout per individual block erase 2 Typical timeout for full chip erase 2 N Max. timeout for word write 2 Max. timeout for buffer write 2 Max. timeout per individual block erase 2 Max. timeout for full chip erase 2 Am41LV3204M Description Description pin present) pin present µ ...
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... Number of Erase Block Regions within device (01h = uniform device, 02h = boot device) Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) Erase Block Region 2 Information (refer to CFI publication 100) Erase Block Region 3 Information (refer to CFI publication 100) Erase Block Region 4 Information (refer to CFI publication 100) Am41LV3204M Description N June 10, 2003 ...
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... The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the erase-suspend-read mode, after Am41LV3204M AC Characteristics section for 25 ...
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... SecSi Sector is en- abled. Word Program Command Sequence Programming is a four-bus-cycle operation. The pro- gram command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written Am41LV3204M A7:A0 (x16) 00h 01h 0Eh 0Fh ...
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... Write Buffer Programming operation. The device then begins programming. Data polling should be used while monitoring the last address location loaded into the write buffer. DQ7, DQ6, DQ5, and DQ1 should be monitored to determine the device status during Write Buffer Programming. Am41LV3204M –A . All subsequent ad- MAX ...
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... WP#/ACC pin has internal pullup Figure 5 illustrates the algorithm for the program oper- ation. Refer to the tions table in the AC Characteristics section for parameters, and Figure 17 for timing diagrams. Am41LV3204M for operations HH Flash Erase and Program Opera- June 10, 2003 ...
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... Yes No Yes Yes No PASS Am41LV3204M Notes: 1. When Sector Address is specified, any address in the selected sector is acceptable. However, when loading Write-Buffer address locations with data, all addresses must fall within the selected Write-Buffer Page. 2. DQ7 may change simultaneously with DQ5. ...
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... Program Suspend mode and continue the programming opera- tion. Further writes of the Resume command are ig- nored. Another Program Suspend command can be written after the device has resume programming. Am41LV3204M Write Operation Status for more June 10, 2003 ...
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... The system must rewrite the command se- quence and any additional addresses and commands. The system can monitor DQ3 to determine if the sec- tor erase timer has timed out (See the section on DQ3: Am41LV3204M section for infor- Flash Erase and Program Opera- 10 ...
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... Further writes of the Resume com- mand are ignored. Another Erase Suspend command can be written after the chip has resumed erasing. Am41LV3204M Write Operation Status section for infor- Write Operation Status section for more ...
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... The Erase Suspend command is valid only during a sector erase section for operation. 16. The Erase Resume command is valid only during the Erase Suspend mode. 17. Command is valid when device is ready to read array data or when device is in autoselect mode. Am41LV3204M ) IH Fourth Fifth Sixth Addr ...
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... Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 16. The Erase Resume command is valid only during the Erase Suspend mode. 17. Command is valid when device is ready to read array data or when device is in autoselect mode. Am41LV3204M ) IL Fourth Fifth Sixth Addr ...
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... During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Figure 8. Data# Polling Algorithm Am41LV3204M section shows the Data# Yes No Yes Yes ...
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... Toggle Bit I on DQ6. Figure 9 shows the toggle bit algorithm. Figure 21 in the “AC Characteristics” section shows the toggle bit timing diagrams. Figure 22 shows the differences be- tween DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit Am41LV3204M II. June 10, 2003 ...
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... DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cy- cles, determining the status as described in the previ- ous paragraph. Alternatively, it may choose to perform Am41LV3204M Table 11 to compare out- RY/BY#: Ready/Busy# sub- ...
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... DQ6 (Note 1) DQ7# Toggle 0 0 Toggle 0 Invalid (not allowed toggle 0 DQ7# Toggle 0 DQ7# Toggle 0 DQ7# Toggle 0 Am41LV3204M Sector Erase Command Write Buffer DQ2 DQ3 (Note 2) DQ1 RY/BY# N/A No toggle 0 1 Toggle N/A Data N/A Toggle N/A Data ...
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... Note: Operating ranges define those limits between which the functionality of the device is guaranteed. June 10, 2003 +0.8 V –0.5 V –2.0 V Figure 10 +0 –2.0 V for SS Figure 11. Am41LV3204M Maximum Negative Overshoot Waveform Maximum Positive Overshoot Waveform 39 ...
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... 4.0 mA min –2.0 mA min I = –100 µ min is ± 5.0 µ max Am41LV3204M Min Typ Max Unit 1.0 µA 35 µA 35 µA 1.0 µ µ µ ...
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... OH CE1 CE2 = V , Other IH IL inputs = CE1#s V – 0.2 V, CE2 V – 0.2 V (CE1#s controlled) or CE2 0.2 V (CE2s controlled) Other input = CIOs = Am41LV3204M Min Typ Max Unit –1.0 1.0 µA –1.0 1.0 µ 0.4 V 2 µA ...
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... Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels INPUTS Steady Changing from Changing from Does Not Apply Center Line is High Impedance State (High Z) Measurement Level Am41LV3204M All Speeds Unit 1 TTL gate 0.0–3 ...
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... Test Setup CE Read Toggle and Data# Polling t RC Addresses Stable t ACC OEH t CE HIGH Z Figure 14. Read Operation Timings Am41LV3204M Speed Min 100 Max 100 IL Max 100 IL Max 30 Max 30 Max 30 Max 30 Min 0 Min 0 Min 10 ...
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... AC CHARACTERISTICS A20-A2 A1-A0 Data Bus CE#f OE Same Page PACC PACC t ACC Qa Qb Figure 15. Page Read Timings Am41LV3204M PACC Qc Qd June 10, 2003 ...
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... CE#f, OE# RESET# CE#f, OE# RESET# June 10, 2003 Description Max Min Min Min Ready Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms t RP Figure 16. Reset Timings Am41LV3204M Speed Unit 500 ns 500 ...
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... Not 100% tested. 2. See the “AC Characteristics” section for more information. 3. For 1–16 words programmed. 4. Effective write buffer specification is based upon a 16-word write buffer operation Per Word Per Word Am41LV3204M Speed Unit Min 100 ns Min 0 ...
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... June 10, 2003 WPH A0h is the true data at the program address. OUT Figure 17. Program Operation Timings Am41LV3204M Read Status Data (last two cycles WHWH1 D Status OUT VHH 47 ...
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... These waveforms are for the word mode. Figure 19. Chip/Sector Erase Operation Timings 555h for chip erase WPH t DH 55h 30h 10 for Chip Erase Am41LV3204M Read Status Data WHWH2 In Complete Progress June 10, 2003 ...
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... Note Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. Figure 20. Data# Polling Timings (During Embedded Algorithms) June 10, 2003 Complement Complement Status Data Status Data Am41LV3204M VA High Z True Valid Data High Z True Valid Data 49 ...
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... AHT t ASO t CEPH t OEPH t OE Valid Valid Status Status (first read) (second read) Enter Erase Suspend Program Erase Suspend Read Program Figure 22. DQ2 vs. DQ6 Am41LV3204M Valid Status (stops toggling) Erase Resume Erase Erase Suspend Read June 10, 2003 Valid Data Erase Complete ...
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... VIDR CE# WE# Figure 23. Temporary Sector Group Unprotect Timing Diagram June 10, 2003 Min Min Program or Erase Command Sequence t RSP Am41LV3204M All Speed Options Unit 500 ns 4 µ VIDR ...
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... For sector group protect, A6–A0 = 0xx0010. For sector group unprotect, A6–A0 = 1xx0010. Figure 24. Sector Group Protect and Unprotect Timing Diagram Valid* Valid* 60h Sector Group Protect: 150 µs, Sector Group Unprotect Am41LV3204M Valid* Verify 40h Status June 10, 2003 ...
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... Not 100% tested. 2. See the “AC Characteristics” section for more information. 3. For 1–16 words programmed. 4. Effective write buffer specification is based upon a 16-word write buffer operation. June 10, 2003 Per Word Per Word Am41LV3204M Speed Unit Min 100 ns Min 0 ...
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... Data# Polling GHEL t t WHWH1 CPH t BUSY for program PD for program 55 for erase 30 for sector erase 10 for chip erase is the data written to the device. OUT Operation Timings Am41LV3204M PA DQ7# D OUT June 10, 2003 ...
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... CE2s = WE June 10, 2003 Min Max Max Max Max Min Min Min Max Max Max Min UB#s and/or LB Am41LV3204M Speed Option Unit ...
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... CO1 t CO2 OLZ t BLZ t LZ Data Valid Figure 27. SRAM Read Cycle (Max.) is less than t (Min.) both for a given device and from device Am41LV3204M BHZ t OHZ June 10, 2003 ...
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... Note (See Note (See Note 3) High-Z t WHZ applied in case a write ends as CE1#s or WE# going high low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when Am41LV3204M Speed Option Unit ...
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... (See Note 5) High-Z applied in case a write ends as CE1#s or WE# going high low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when Am41LV3204M t (See Note Data Valid High-Z is measured from the beginning of write ...
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... AS t (See Note 4) WP (See Note 5) High-Z applied in case a write ends as CE1#s or WE# going high low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when Am41LV3204M t (See Note Data Valid High-Z is measured from the beginning of write ...
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... Per Byte 7.5 Per Word 15 200 Per Byte 6.25 Per Word 12.5 31.5 = 3.0, worst case temperature. Maximum values are valid up to and including 100,000 CC = 3.0 V, one pin at a time. CC Am41LV3204M Unit Comments 3.5 sec Excludes 00h programming prior to erasure (Note 6) 64 sec 600 µs 600 µs 540 µ ...
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... DATA RETENTION Parameter Description Minimum Pattern Data Retention Time June 10, 2003 Test Setup Fine-Pitch BGA Fine-Pitch BGA OUT Fine-Pitch BGA IN Test Conditions 150 C 125 C Am41LV3204M Typ Max Unit 4.2 5.0 pF 5.4 6.5 pF 3.9 4.7 pF Min Unit 10 Years 20 Years 61 ...
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... CE1#s V – 0.2 V (Note 3.0 V, CE1 (Note 1) See data retention waveforms – 0.2 V (CE1#s controlled) or CE2s 0.2 V (CE2s controlled). Data Retention Mode t SDR CE1#s V Data Retention Mode t SDR CE2#s < 0.2 V Am41LV3204M Min Typ Max 2.7 3.3 – 0 (Note RDR - 0 RDR ...
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Sales Offices and Representatives North America ALABAMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... IN THE OUTER ROW E/2 BALL PITCH 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. SOLDER BALL PLACEMENT 9. NOT USED. DEPOPULATED SOLDER BALLS 10. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. Am41LV3204M ...
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... ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. June 10, 2003 Connection Diagram Corrected pinout numbering. Pin Description Added CIOf and DQ15/A-1 Am41LV3204M 65 ...
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... Am41LV3204M June 10, 2003 ...