zic2410 California Eastern Laboratories, zic2410 Datasheet - Page 37

• Manufacturer Part Number: zic2410
• Description: Single-chip Solution, Compliant With Zigbee
• Manufacturer: California Eastern Laboratories

INTID
FCR (UART1 FIFO CONTROL REGISTER, 0x2512)
Note: FCR register uses the same address as IIR register in Table 20 above. IIR register is read-only
and FCR register is write-only.
LCR (UART1 LINE CONTROL REGISTER, 0x2513)
011
010
110
001
000
Bit
7:6
5:3
2
1
0
7
6
5
4
3
2
Rev A
URXFRST
UTXFRST
URXFTRI
Name
DLAB
Priority
PEN
EPS
STB
SB
SP
G
4th
2
2
3
1
nd
nd
st
rd
Trigger Level of Receiver FIFO. Interrupt occurs when FIFO
receives the the number of data bytes based on this field’s value
below. For example, when URXFTRIG field is set to ‘3’, interrupt
does not occur until FIFO receives 14 bytes.
Reserved
When this field is set to ‘1’, Transmitter FIFO is cleared and the
circuits related to it are reset.
When this field is set to ‘1’, Receiver FIFO is cleared and the
circuits related to it are reset.
Reserved
Divisor Latch Access Enable. When this field is set to ‘1’, Divisor
register (DLM, DLL) can be accessed. When this field is set to ‘0’,
general register can be accessed.
Set Break. When this field is set to ‘1’, serial output is forced to be
‘0’ (break state)
Stick Parity. When PEN and EPS are ‘1’ with this field set to ‘1’, a
parity of ‘0’ is transmitted. In reception mode, it checks whether
parity value is ‘0’ or not. When PEN is ‘1’ and EPS is ‘0’ with this
field is to ‘1’, parity of ‘1’, is transmitted. In reception mode, it
checks whether parity value is ‘1’ or not.
Even Parity Enable. When this field is set to ‘1’, parity value is
even. When set to ‘0’, parity value is odd.
Parity Enable. When this field is set to ‘1’, parity is calculated for
the byte to be transmitted and transferred with it. In reception
mode, checks parity. When this field is ‘0’, parity is not generated.
Number of Stop Bits. When this field is set to ‘1’, 2 stop bit is
used. When transmitting a word (character) of 5 bit length, 1.5 stop
bit is used. When this field is ‘0’, 1 stop bit is used.
Receiver Line Status
Transmitter Holding
Timeout Indication
Register Empty
Interrupt Type
Modem Status
Receiver Data
0: 1byte
1: 4 bytes
2: 8 bytes
3: 14 bytes
available
Table 22 – UART1 Control Registers
Document No. 0005-05-07-00-000
ZIC2410 Datasheet
There is at least 1 character in
been input to the FIFO or read
the FIFO but no character has
from it for the last 4 character
Transmitter Holding Register
Descriptions
Parity, Overrun or Framing
FIFO trigger level reached
errors or Break Interrupt
CTS, DSR, RI or DCD
Interrupt Source
Empty
times.
Writing to the Transmitter
FIFO drops below trigger
Interrupt Reset Control
Reading from the FIFO
Reading the LSR (Line
Reading the Modem
Holding Register or
Status Register).
(Receiver Buffer
status register
reading IIR
Register)
level
R/W
W/O
W/O
W/O
W/O
W/O
R/W
R/W
R/W
R/W
R/W
R/W
Page 37 of 119
Reset
Value
3
0
0
0
0
0
0
0
0
0
0