89hpes24t6zgbxg Integrated Device Technology, 89hpes24t6zgbxg Datasheet - Page 7

• Manufacturer Part Number: 89hpes24t6zgbxg
• Description: 24-lane, 6-port Pcie I/o Expansion Switch
• Manufacturer: Integrated Device Technology

IDT 89HPES24T6 Data Sheet
JTAG_TRST_N
SWMODE[3:0]
P45MERGEN
JTAG_TCK
JTAG_TDO
JTAG_TMS
JTAG_TDI
RSTHALT
Signal
PERSTN
Signal
Type
Type
O
I
I
I
I
I
I
I
I
Port 4 and 5 Merge. P45MERGEN is an active low signal. It is pulled low
internally via a 251K ohm resistor.
When this pin is low, port 4 is merged with port 5 to form a single x8 port.
The Serdes lanes associated with port 5 become lanes 4 through 7 of port
4. When this pin is high, port 4 and port 5 are not merged, and each oper-
ates as a single x4 port.
Fundamental Reset. Assertion of this signal resets all logic inside the
PES24T6 and initiates a PCI Express fundamental reset.
Reset Halt. When this signal is asserted during a PCI Express fundamental
reset, the PES24T6 executes the reset procedure and remains in a reset
state with the Master and Slave SMBuses active. This allows software to
read and write registers internal to the device before normal device opera-
tion begins. The device exits the reset state when the RSTHALT bit is
cleared in the SWCTL register by an SMBus master.
Switch Mode. These configuration pins determine the PES24T6 switch
operating mode. These pins should be static and not change after the
negation of PERSTN.
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM initialization
0x2 - through 0xF Reserved
JTAG Clock. This is an input test clock used to clock the shifting of data
into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is
independent of the system clock with a nominal 50% duty cycle.
JTAG Data Input. This is the serial data input to the boundary scan logic or
JTAG Controller.
JTAG Data Output. This is the serial data shifted out from the boundary
scan logic or JTAG Controller. When no data is being shifted out, this signal
is tri-stated.
JTAG Mode. The value on this signal controls the test mode select of the
boundary scan logic or JTAG Controller.
JTAG Reset. This active low signal asynchronously resets the boundary
scan logic and JTAG TAP Controller. An external pull-up on the board is
recommended to meet the JTAG specification in cases where the tester
can access this signal. However, for systems running in functional mode,
one of the following should occur:
Table 5 System Pins (Part 2 of 2)
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
Table 6 Test Pins
7 of 33
Name/Description
Name/Description
April 23, 2008