89hpes24t6zgbxg Integrated Device Technology, 89hpes24t6zgbxg Datasheet - Page 4

• Manufacturer Part Number: 89hpes24t6zgbxg
• Description: 24-lane, 6-port Pcie I/o Expansion Switch
• Manufacturer: Integrated Device Technology

Pin Description
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
IDT 89HPES24T6 Data Sheet
The following tables list the functions of the pins provided on the PES24T6. Some of the functions listed may be multiplexed onto the same pin.
PEREFCLKN[2:1]
PEREFCLKP[2:1]
PE0RN[3:0]
PE1RN[3:0]
PE2RN[3:0]
PE3RN[3:0]
PE4RN[3:0]
PE5RN[3:0]
PE0RP[3:0]
PE0TP[3:0]
PE0TN[3:0]
PE1RP[3:0]
PE1TP[3:0]
PE1TN[3:0]
PE2RP[3:0]
PE2TP[3:0]
PE2TN[3:0]
PE3RP[3:0]
PE3TP[3:0]
PE3TN[3:0]
PE4RP[3:0]
PE4TP[3:0]
PE4TN[3:0]
PE5RP[3:0]
PE5TP[3:0]
PE5TN[3:0]
REFCLKM
Signal
Type
O
O
O
O
O
O
I
I
I
I
I
I
I
I
PCI Express Port 0 Serial Data Receive. Differential PCI Express receive
pairs for port 0. Port 0 is the upstream port.
PCI Express Port 0 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 0. Port 0 is the upstream port.
PCI Express Port 1 Serial Data Receive. Differential PCI Express receive
pairs for port 1. When port 0 is merged with port 1, these signals become
port 0 receive pairs for lanes 4 through 7.
PCI Express Port 1 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 1. When port 0 is merged with port 1, these signals
become port 0 transmit pairs for lanes 4 through 7.
PCI Express Port 2 Serial Data Receive. Differential PCI Express receive
pairs for port 2.
PCI Express Port 2 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 2.
PCI Express Port 3 Serial Data Receive. Differential PCI Express receive
pairs for port 3. When port 2 is merged with port 3, these signals become
port 2 receive pairs for lanes 4 through 7.
PCI Express Port 3 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 3. When port 2 is merged with port 3, these signals
become port 2 transmit pairs for lanes 4 through 7.
PCI Express Port 4 Serial Data Receive. Differential PCI Express receive
pairs for port 4.
PCI Express Port 4 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 4.
PCI Express Port 5 Serial Data Receive. Differential PCI Express receive
pairs for port 5. When port 4 is merged with port 5, these signals become
port 4 receive pairs for lanes 4 through 7.
PCI Express Port 5 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 5. When port 4 is merged with port 5, these signals
become port 4 transmit pairs for lanes 4 through 7.
PCI Express Reference Clock. Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the dif-
ferential reference clock is determined by the REFCLKM signal.
PCI Express Reference Clock Mode Select. This signal selects the fre-
quency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
Table 2 PCI Express Interface Pins
4 of 33
Name/Description
April 23, 2008