zl50073 Zarlink Semiconductor, zl50073 Datasheet - Page 14

• Manufacturer Part Number: zl50073
• Description: 32 K Channel Digital Switch With High Jitter Tolerance, Rate Conversion Per Group Of 4 Streams 8, 16, 32 Or 64 Mbps
• Manufacturer: Zarlink Semiconductor

Pin Description (continued)
1.0
1.1
The device has 128 ST-BUS/GCI-Bus inputs (STiA0 - 31, STiB0 - 31, STiC0 - 31, STiD0 - 31) and 128
ST-BUS/GCI-Bus outputs (SToA0 - 31, SToB0 - 31, SToC0 - 31, SToD0 - 31). It is a non-blocking digital switch with
32,768 64 kbps channels and is capable of performing rate conversion between groups of 4 inputs and 4 outputs.
The inputs accept serial input data streams with data rates of 8.192 Mbps, 16.384 Mbps, 32.768 Mbps or
65.536 Mbps. There are 32 input groups with each group consisting of 4 streams (‘A’, ‘B’, ‘C’ and ‘D’). Each group
can be set to any of the data rates. The outputs deliver serial data streams with data rates of 8.192 Mbps,
16.384 Mbps, 32.768 Mbps or 65.536 Mbps. There are 32 output groups with each group consisting of 4 streams
(‘A’, ‘B’, ‘C’ and ‘D’). Each group can be set to any of the data rates.
By using Zarlink’s message mode capability, the microprocessor can store data in the connection memory which
can be broadcast to the output streams on a per-channel basis. This feature is useful for transferring control and
status information for external circuits or other ST-BUS/GCI-Bus devices.
Overview
Functional Description
D18
C19
A20
B21
A22
E17
Pin
B7
Name
TRST
D16B
PWR
TMS
TCK
TDo
TDi
IEEE 1149.1 Test Access Port (TAP)
Zarlink Semiconductor Inc.
Microprocessor Port Bus 16/32 Bit Mode Select (5 V Tolerant
Input with Internal Pull-down)
Control input:
0 = 32 bit data bus
1 = 16 bit data bus
Device Reset (5 V Tolerant Schmitt-Triggered Input)
Asynchronous reset input used to initialize the ZL50073.
0 = Reset
1 = Normal
See Section 11.0, Power-up and Initialization of the ZL50073 for
detailed description of Reset state.
Test Data (5 V Tolerant Input with Internal Pull-up)
Serial test data input. When not used, this input may be left
unconnected.
Test Data (3.3 V Output)
Serial test data output.
Test Clock (5 V Tolerant Schmitt-Triggered Input with Internal
Pull-up)
Provides the clock to the JTAG test logic
Test Reset (5 V Tolerant Schmitt-Triggered Input with Internal
Pull-up)
Asynchronously initializes the JTAG TAP controller by putting it in
the Test-Logic-Reset state. This pin should be pulsed low during
power-up to ensure that the device is in the normal functional
mode. When JTAG is not being used, this pin should be pulled low
during normal operation.
Test Mode Select (5 V Tolerant Input with Internal Pull-up)
JTAG signal that controls the state transitions of the TAP controller.
When not used, this pin is pulled high by an internal pull-up resistor
and may be left unconnected.
ZL50073
14
Description
Data Sheet