msm7586-01 Oki Semiconductor, msm7586-01 Datasheet - Page 10

• Manufacturer Part Number: msm7586-01
• Description: Shift Qpsk Modem/adpcm Codec
• Manufacturer: Oki Semiconductor

¡ Semiconductor
AFC
AFC operation range specification signal input.
As shown in Fig. 4, the AFC information is reset when both AFC and RPR are set to "1". AFC
operation starts after a fixed number of clock cycles and the AFC information is reset. If RPR is
set to "1", an average number of times that AFC turns on is low. If RPR is "0", AFC is high. If AFC
is "0", frequency error is not calculated, but the frequency is corrected using an error that is held.
RCW
Clock recovery circuit operation ON/OFF control signal input.
If RCW this pin is "0", DPLL does not make any phase corrections.
DENM , EXCKM, DINM, DOUTM
Serial control ports for the microprocessor interface.
The device contains a 6-byte control register (CRM0 - 5). An external CPU uses these pins to read
data from and write data to the control register. DENM is the "Enable" signal input pin. EXCKM
is a data shift clock pulse input pin. DINM is an address and data input pin. DOUTM is a data
output pin. Figure 5 shows input/output timing diagram.
(CASE1)
(CASE2)
AFC
RPR
AFC
RPR
AFC information
is reset.
The clock recovery circuit
starts with the previous
AFC information.
Figure 4 AFC Control Timing Diagram
Average
number of times
AFC is low.
"0"
Average number of times
AFC is high.
Average number of times
AFC is high.
MSM7586-01/03
AFC information
is maintained.
AFC information
is maintained.
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