73k322l ETC-unknow, 73k322l Datasheet - Page 6

• Manufacturer Part Number: 73k322l
• Description: Ccitt V.23, V.22, V.21 Single-chip Modem
• Manufacturer: ETC-unknow

CCITT V.23, V.22, V.21
Single-Chip Modem
RS-232 INTERFACE
NAME
RXCLK
RXD
TXCLK
TXD
ANALOG INTERFACE AND OSCILLATOR
RXA
TXA
XTL1
XTL2
PIN NUMBER
PLCC/DIP
23
22
18
21
27
16
(continued)
2
3
TYPE
O
O
O
O
I
I
I
I
DESCRIPTION
Receive Clock. The falling edge of this clock output is coincident with
the transitions in the serial received DPSK data output. The rising
edge of RXCLK can be used to latch the valid output data. RXCLK
will be valid as long as a carrier is present. In V.23 or V.21 mode a
clock which is 16 x 1200 (or 16 x 75) or 16 x 300 Hz baud data rate is
output, respectively, for driving a UART.
Received Data Output. Serial receive data is available on this pin.
The data is always valid on the rising edge of RXCLK when in
Synchronous mode. RXD will output constant marks if no carrier is
detected.
Transmit Clock. This signal is used only in synchronous DPSK
transmission to latch serial input data on the TXD pin. Data must be
provided so that valid data is available on the rising edge of the
TXCLK. The transmit clock is derived from different sources
depending upon the Synchronization mode selection. In Internal
Mode the clock is 1200 Hz generated internally. In External Mode
TXCLK is phase locked to the EXCLK pin. In Slave Mode TXCLK is
phase locked to the RXCLK pin. TXCLK is always active. In V.23 or
V.21 mode the output is a 16 x 1200 (or 16 x 75) or 16 x 300 Hz baud
clock, respectively for driving a UART.
Transmit Data Input. Serial data for transmission is applied on this
pin. In Synchronous modes, the data must be valid on the rising
edge of the TXCLK clock. In Asynchronous modes (1200 or 300
baud) no clocking is necessary. DPSK must be 1200/600 bit/s +1%, -
2.5% or +2.3%, -2.5% in Extended Overspeed mode.
Received modulated analog signal input from the telephone line
interface.
Transmit analog output to the telephone line interface.
These pins are for the internal crystal oscillator requiring a 11.0592
MHz Parallel mode crystal and two load capacitors to Ground. XTL2
can also be driven from an external clock.
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