73k322l ETC-unknow, 73k322l Datasheet - Page 5

• Manufacturer Part Number: 73k322l
• Description: Ccitt V.23, V.22, V.21 Single-chip Modem
• Manufacturer: ETC-unknow

PARALLEL MICROPROCESSOR CONTROL INTERFACE
NAME
WR
SERIAL MICROPROCESSOR CONTROL INTERFACE
AD0-AD2
AD7
RD
WR
Note:
DTE USER INTERFACE
NAME
EXCLK
The Serial Control mode is provided by tying ALE high and CS low. In this configuration AD7 becomes
the data input and AD0, AD1 and AD2 become the address only. See Serial Control timing diagrams on
pages 22 and 23.
PIN NUMBER
PIN NUMBER
PLCC/DIP
PLCC/DIP
4-6
13
11
14
13
19
TYPE
TYPE
I/O
I
I
I
I
I
DESCRIPTION
Write. A low on this informs the 73K322L that data is available on
AD0-AD7 for writing into an internal register. Data is latched on the
rising edge of WR . No data is written unless both WR and the latched
CS are low.
Register Address Selection. These lines carry register addresses and
should be valid during any read or write operation.
Serial Control Data Input/Output. Data for a read/write operation is
clocked in or out on the falling edge of the EXCLK pin. The direction
of data flow is controlled by the RD pin. RD low outputs data. RD high
inputs data.
Read. A low on this input informs the 73K322L that data or status
information is being read by the processor. The falling edge of the RD
signal will initiate a read from the addressed register. The RD signal
must continue for eight falling edges of EXCLK in order to read all
eight bits of the referenced register. Read data is provided LSB first.
Data will not be output unless the RD signal is active.
Write. A low on this input informs the 73K322L that data or status
information has been shifted in through the DATA pin and is available
for writing to an internal register. The normal procedure for a write is
to shift in data LSB first on the DATA pin for eight consecutive falling
edges of EXCLK and then to pulse WR low. Data is written on the
rising edge of WR .
DESCRIPTION
External Clock. This signal is used only in synchronous DPSK
transmission when the external timing option has been selected. In
the External Timing mode the rising edge of EXCLK is used to strobe
synchronous DPSK transmit data available on the TXD pin. Also used
for serial control interface.
5
(continued)
CCITT V.23, V.22, V.21
Single-Chip Modem