wm8215 Wolfson Microelectronics plc, wm8215 Datasheet - Page 26

• Manufacturer Part Number: wm8215
• Description: 60msps 10-bit 3-channel Ccd Digitiser
• Manufacturer: Wolfson Microelectronics plc

ADDRESS
000111
(07h)
001000
(08h)
WM8215
w
<A5:A0>
Setup Register
5
Setup Register
6
REGISTER
BIT
3:2
7:4
4:0
NO
1
0
1
2
3
4
5
6
7
5
6
7
CLAMPCTRL
VRLCDACPD
ADCREFPD
INTM[1:0]
Reserved
Reserved
NAME(S)
Not Used
Not Used
RLCEN
REDPD
GRNPD
ADCPD
VRXPD
BLUPD
ACYC
BIT
DEFAULT
00000
0000
00
0
1
0
0
0
0
0
0
0
0
0
0
When LINEBYLINE = 0 this bit has no effect.
When LINEBYLINE = 1 this bit determines the function of
the RSMP input pin and the offset/gain register controls.
0 = RSMP pin enabled for either reset sampling (CDS) or
Reset Level Clamp control. Internal selection of gain/offset
multiplexers using INTM[1:0] register bits.
1 = Auto-cycling enabled by pulsing the RSMP input pin.
This means that each time a pulse is applied to this pin the
single input channel will switch to the next offset register
and gain register in the sequence. The sequence is
Red->Green->Blue->Red… offset and gain registers
applied to the red input channel.
When auto-cycling is enabled, the RSMP pin alone cannot
be used to control reset level clamping. Reset level
clamping may be enabled in this situation by setting the
CLAMPCTRL and RLCEN bits so that he logical AND of
RSMP and VSMP closes the clamp switch.
When auto-cycling is enabled, the RSMP pin cannot be
used for reset sampling (i.e. CDS must be set to 0).
When LINEBYLINE=0 or ACYC=1 this bit has no effect.
When LINEBYLINE=1 and ACYC=0:
Controls the PGA/offset mux selector:
00 = Red PGA/Offset registers applied to input channel
01 = Green PGA/Offset registers applied to input channel
10 = Blue PGA/Offset registers applied to input channel
11 = Reserved.
Must be set to 0
When set powers down red S/H, PGA
When set powers down green S/H, PGA
When set powers down blue S/H, PGA
When set powers down ADC. Allows reduced power
consumption without powering down the references which
have a long time constant when switching on/off due to the
external decoupling capacitors.
When set powers down 4-bit RLCDAC, setting the output
to a high impedance state and allowing an external
reference to be driven in on the VRLC/VBIAS pin.
When set disables VRT, VRB buffers to allow external
references to be used.
When set disables VRX buffer to allow an external
reference to be used.
Must be set to 0
Must be set to 0
Reset Level Clamp Enable. When set Reset Level
Clamping is enabled. The method of clamping is
determined by CLAMPCTRL.
0 = RLC switch is controlled directly from RSMP input pin:
1 = RLC switch is controlled by logical combination of
RSMP and VSMP.
Must be set to 0
RSMP = 0: switch is open
RMSP = 1: switch is closed
RSMP && VSMP = 0: switch is open
RSMP && VSMP = 1: switch is closed
DESCRIPTION
PD, Rev 4.2, February 2009
Production Data
26