ak4527b AKM Semiconductor, Inc., ak4527b Datasheet - Page 20

• Manufacturer Part Number: ak4527b
• Description: High Performance Multi-channel Audio Codec
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
n Power-Down
The ADC and DACs of AK4527B are placed in the power-down mode by bringing PDN “L” and both digital filters are
reset at the same time. PDN “L” also reset the control registers to their default values. In the power-down mode, the
analog outputs go to VCOM voltage and DZF1-2 pins go to “L”. This reset should always be done after power-up. In case
of the ADC, an analog initialization cycle starts after exiting the power-down mode. Therefore, the output data, SDTO
becomes available after 522 cycles of LRCK clock. In case of the DAC, an analog initialization cycle starts after exiting
the power-down mode. The analog outputs are VCOM voltage during the initialization. Figure 6 shows the power-up
sequence.
The ADC and DACs can be powered-down individually by PWADN and PWDAN bits. In this case, the internal register
values are not initialized. When PWADN = “0”, SDTO goes to “L”. When PWDAN = “0”, the analog outputs go to
VCOM voltage and DZF1-2 pins go to “H”. Because some click noise occurs, the analog output should muted externally
if the click noise influences system application.
Notes:
MS0056-E-00
(1) The analog part of ADC is initialized after exiting the power-down state.
(2) The analog part of DAC is initialized after exiting the power-down state.
(3) Digital output corresponding to analog input and analog output corresponding to digital input have the group delay
(4) ADC output is “0” data at the power-down state.
(5) Click noise occurs at the end of initialization of the analog part. Please mute the digital output externally if the click
(6) Click noise occurs at the falling edge of PDN and at 512/fs after the rising edge of PDN.
(7) When the external clocks (MCLK, BICK and LRCK) are stopped, the AK4527B should be in the power-down
(8) DZF pins are “L” in the power-down mode (PDN = “L”).
(9) Please mute the analog output externally if the click noise (6) influences system application.
(10) DZF= “L” for 10 11/fs after PDN= “ ”.
(GD).
noise influences system application. Required muting time depends on the configuration of the input buffer circuits.
mode.
Clock In
MCLK,LRCK,SCLK
DZF1/DZF2
DAC Internal
DAC In
DAC Out
ADC Internal
ADC In
ADC Out
External
PDN
(Digital)
(Analog)
(Analog)
(Digital)
Mute
State
State
Figure 12,13: 1s
Figure 14,15: 200ms
Normal Operation
Normal Operation
(9)
Figure 6. Power-down/up sequence example
GD
GD
(3)
(3)
(6)
(8)
(7)
Power-down
Power-down
Don’t care
“0”data
“0”data
- 20 -
(4)
Mute ON
10 11/fs (10)
Init Cycle
516/fs
Init Cycle
522/fs
(2)
(1)
(6)
(5)
Normal Operation
Normal Operation
GD
GD
[AK4527B]
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