hsp50110 Intersil Corporation, hsp50110 Datasheet - Page 19

• Manufacturer Part Number: hsp50110
• Description: Digital Quadrature Tuner
• Manufacturer: Intersil Corporation

POSITION
POSITION
31-11
20-19
22-21
17-6
BIT
BIT
5-4
5-0
10
18
0
1
2
3
6
7
8
9
Input Format
Input Mode
Serial/Parallel Output
Select
Test Enable
Serial Output Clock
Select
Serial Output Mode
Serial Output Word
Orientation
Output Data Format
DATARDY Polarity
Output Clock Polarity
CIC Shifter Gain
Programmable
Divider
Programmable
Divider Clock Source
CIC Filter
Configuration
Compensation
Filtering
FUNCTION
FUNCTION
19
TABLE 10. DECIMATING FILTER CONFIGURATION REGISTER
0 = Two’s complement input format, 1 = Offset binary input format.
Note: if a real input with offset binary weighting is used, the unused quadrature input pins should be tied
to 1000000000.
0 = Input Controller operates in Interpolated Input Mode.
1 = Input Controller operates in Gated Input Mode.
(See Input Controller Section).
1 = Serial Output, 0 = Parallel Output. (See Output Formatter Section).
0 = Test Mode Disabled, 1 = Test Mode Enabled. (See Test Mode Section).
Bits 5-4
(See Output Formatter Section).
1 = I Followed by Q Mode, 0 = Simultaneous I and Q Mode. (See Output Formatter Section)
1 = MSB First, 0 = LSB First.
1 = Offset Binary, 0 = Two’s Complement.
1 = Active Low, 0 = Active High.
This applies to both serial and parallel output modes. (See Output Formatter Section).
1 = High to Low clock transition at midsample.
0 = Low to High clock transition at midsample.
Reserved.
These 6 bits set the fixed gain of the CIC shifter. The gain factor is of the form, 2
stored in this location. A gain range from 2
at the input to the CIC FIlter, care must be taken so that the signal is not shifted outside of the input bit
range of the filter. (See Gain Distribution Section).
These 12 bits specify the divisor for the programmable divider in the Re-Sampler. The actual divisor is
equal to the 12-bit value +1 for a total range of 1 to 4096. For example, a value of 7 would produce a
sampling rate of 1/8 the CLK or 1/8 the carry-out frequency of the Re-Sampler NCO depending on con-
figuration.
(See Re-Sampler).
1 = Divider clocked at sample rate of data input to the Low Pass Filter.
0 = Divider clocked by Re-Sampler NCO.
(See Re-Sampler).
0 0
0 1
1 X
When a 3 stage CIC filter is chosen, a decimation factor >3 must be used if the Re-Sampler NCO is used
to set the output sampling rate. (See Re-Sampler Section and Low Pass Filtering Section).
0 0 x/sinx filtering.
0 1 (x/sinx)
1 X bypass compensation filter.
(See Low Pass Filtering Section).
0 0
0 1
1 0
1 1
3 stage CIC filter.
1 stage CIC (Integrate and dump) filter.
bypass CIC.
TABLE 9. I/O FORMATTING/CONTROL
3
filtering.
Serial Output Clock Rate
DESTINATION ADDRESS = 4
DESTINATION ADDRESS = 5
CLK (Serial Output Clock Pin = High)
Clk/2
CLK/4
CLK/8
CLK
ReSampler
HSP50110
SOURCE
PROGRAMMABLE DIVIDER RANGE
0
to 2
DESCRIPTION
DESCRIPTION
63
is provided. Since the CIC shifter sets the signal level
1-4096
2-4096
N
, where N is the valued