hsp50214b Intersil Corporation, hsp50214b Datasheet - Page 37

• Manufacturer Part Number: hsp50214b
• Description: Programmable Downconverter
• Manufacturer: Intersil Corporation

The serial direct output can be programmed to output less
than 16-bits. New output data preempts old output data, so if
SERSYNC is programmed to precede the MSB, then data
will shift out until new data comes along. Note that if
SERSYNC is programmed to follow the LSB, then a sync will
never occur.
Buffer RAM Output Port
The Buffer RAM parallel output mode utilizes a RAM to store
output data for future retrieval by either the 8-bit
microprocessor that is configuring the PDC or by a 16-bit
baseband processing engine (which could also be a
microprocessor). Data is output from the RAM only on request
and can be obtained from either the 8-bit μP interface or from
a 16-bit interface that uses the two LSBytes of AOUT and
BOUT. The RAM holds up to eight 80-bit sample sets. Each
sample set includes 16-bits of each I, Q, magnitude, phase,
and frequency data. The RAM samples are mapped as shown
in Table 16. The Buffer RAM controller supports both FIFO
and Snapshot modes.
THE REMAINING CHOICES FOR THE THIRD LINK ON SEROUTB ARE:
LSB WORD0
“NORMAL”
“INVERTED”
“NORMAL”
“INVERTED”
PHASE, FREQUENCY, AGC LEVEL, AND TIMING ERROR
2
1
1
1
0
DATA SHIFT MSB FIRST
SERSYNC PRECEDES MSB
15
0
0
DATA WORD 3
DATA WORD 3
MAGNITUDE
37
SERSYNC FOLLOWS LSB
14
TBD
MSB WORD1
• • •
FIGURE 35. EXAMPLE 2 SERIAL OUTPUT DATA STREAM
FIGURE 36. VALID SERSYNC CONFIGURATION OPTIONS
(3 DATA WORDS IN EACH SERIAL OUTPUT)
2
CONTROL WORD 19, BITS 24-21 = 011
1
2
2
0
DATA WORD 2
DATA WORD 2
MAGNITUDE
15
HSP50214B
1
1
LSB WORD1
Q
14
MSB WORD2
• • •
NOTE: I and Q are sample aligned in time. |r| and
SAMPLE
RAM
SET
0
1
2
3
4
5
6
7
2
aligned in time, but one sample delayed from I or Q. The
frequency sample is delayed in time from I or Q by 1
sample time + 63 tap FIR impulse response. If the FIR is
set to decimate, the FIR output will be repeated every
sample time until a new value appears at the filter output.
(i.e., the frequency samples are clocked out at the I, Q
sample rate regardless of decimation.)
DATA WORD 1
DATA WORD 1
1
NOTE: Once magnitude is identified to follow Q,
TABLE 16. RAM DATA STORAGE MAP
I
I
I
I
I
I
I
I
0
1
2
3
4
5
6
7
DATA
(000)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
3
3
0
Q
I
I
15
it must be that way on both serial outputs.
2
2
LSB WORD2
Q
Q
Q
Q
Q
Q
Q
Q
14
DATA
(001)
0
1
2
3
4
5
6
7
MSB WORD3
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
Q
• • •
|r|
|r|
|r|
|r|
|r|
|r|
|r|
|r|
SEROUTA
SEROUTB
DATA
(010)
0
1
2
3
4
5
6
7
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
|r|
2
φ
φ
φ
φ
φ
φ
φ
φ
DATA
0
1
2
3
4
5
6
7
(011)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
LATE
SERSYNC
MODE
Φ
EARLY
SERSYNC
MODE
φ
are sample
May 1, 2007
f
f
f
f
f
f
f
f
0
1
2
3
4
5
6
7
DATA
(100)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
FN4450.4
F