hsp50214b Intersil Corporation, hsp50214b Datasheet
hsp50214b
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hsp50214b Summary of contents
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... Data Sheet Programmable Downconverter The HSP50214B Programmable Downconverter converts digitized IF data into filtered baseband data which can be processed by a standard DSP microprocessor. The Programmable Downconverter (PDC) performs down conversion, decimation, narrowband low pass filtering, gain scaling, resampling, and Cartesian to Polar coordinate conversion ...
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... Block Diagram MICROPROCESSOR READ/WRITE CONTROL C(7:0) LEVEL DETECT ORDER FILTER IN(13:0) GAIN ORDER ADJ (2:0) FILTER CARRIER COF NCO SOF CLKIN PROCCLK REFCLK 2 HSP50214B AGC LOOP FILTER TH POLYPHASE 5 FIR AND CIC HALFBAND FILTERS TH POLYPHASE 5 FIR AND CIC HALFBAND FILTERS RESAMPLING NCO AGC I OUT CARTESIAN MAG. ...
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... CLKIN 17 GND ENI GAINADJ2 20 GAINADJ1 21 GAINADJ0 22 COF 23 24 COFSYNC GND 25 26 SOF 27 SOFSYNC SYNCIN1 29 30 SYNCIN2 3 HSP50214B HSP50214B (120 LD MQFP) TOP VIEW 90 DATARDY 89 OEBH 88 BOUT15 87 BOUT14 BOUT13 84 BOUT12 83 BOUT11 82 BOUT10 81 BOUT9 80 BOUT8 79 GND 78 GND 77 PROCCLK ...
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... AOUT(15:0) O Parallel Output Bus A. Two parallel output modes are available on the HSP50214B. The first is called the Direct Output Port, where the source is selected through Control Word 20 (see the Microprocessor Write Section) and comes directly from the Output MUX Section (see Output Control Section). The most significant byte of AOUT always outputs the most significant byte of the Parallel Direct Output Port whose data type is selected via μ ...
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... Multiple Chip Sync Output. Provided for synchronizing multiple parts when CLKIN and PROCCLK are asynchronous. MSYNCO is the synchronization signal between the input section operating under CLKIN and the back end processing operating under PROCCLK. This output sync signal from one part is connected to the MSYNCI signal of all the HSP50214Bs. MSYNCI I Multiple Chip Sync Input ...
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... INTERFACE COF NCO COFSYNC (CARRIER TRACKING) SOF SOFSYNC REFCLK MICROPROCESSOR READ/WRITE RD WR CONTROL A(2:0) SECTION C(7:0) FIGURE 1. FUNCTIONAL BLOCK DIAGRAM OF THE HSP50214B PROGRAMMABLE DOWNCONVERTER TO OUTPUT FORMATTER AGCOUT AND MICROPROCESSOR INTERFACE 255-TAP PROGRAMMABLE AGC RE-SAMPLER FIR FILTER (DECIMATE ...
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... Converter, Discriminator, and Output Sections. All of these sections are configured through a microprocessor interface. The HSP50214B has three clock inputs; two are required and one is optional. The input level detector, carrier NCO, and CIC decimating filter sections operate on the rising edge of the input clock, CLKIN ...
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... FIR filter. The PDC offers 0.012Hz resolution on tuning to the desired receive channel and excellent rejection of the portions of the band not being 8 HSP50214B processed, via the halfband and 255-tap programmable, 22- bit coefficient FIR filter. Traditional Modulation Formats AM, ASK, FM AND FSK The PDC has the capability to fully demodulate AM and FM modulated waveforms ...
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... However, if different enabling is desired for the front end and backend processing of the PDC’s, these signals can still be controlled independently. In the HSP50214B, the Control Word 25 reset signal has been extended so that the front end reset is 10 CLKIN periods wide and the back end reset is 10 PROCCLK periods wide ...
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... CIC filter path will not yield the desired 85dB dynamic range band width of 500kHz. FIGURE 4. STATEMENT OF THE PROBLEM 10 HSP50214B programmed via the microprocessor interface, as shown in Figure 9. The bit weighting of the data path through the input threshold detector is shown in Figure 10. The threshold is a signed number should be set to the inverse of the desired input level ...
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... FIGURE 6. INTERPOLATION SPECTRUM: INTERPOLATE BY 8 THE INPUT DATA WITH ZERO STUFFING; SAMPLE AT RATE R = f’s 4MHz 8MHz DECIMATE BY 10 AND CIC FILTER; SAMPLE AT RATE R = f’s/10 85dB DYNAMIC RANGE BANDWIDTH O.5MHz 1MHz FIGURE 7. ALIAS PROFILE AND THE 85dB DYNAMIC RANGE BANDWIDTH INPUT FIGURE 8. PROCESSOR BASED EXTERNAL IF AGC 11 HSP50214B 15MHz 20MHz ...
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... Additionally, in the HSP50214B, the ability to align the start/restart of the input level detector integration period with ...
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... F) CLOSED LOOP STEADY STATE (CONSTANT INPUT) FIGURE 11. SIGNAL PROCESSING WITHIN LEVEL DETECTOR In the HSP50214B, the polarity of the LSB’s of the integration period pre-load is selectable. If Control Word 27, Bit 23 is set to a logic one, the two LSB’s of the integration period preload are set to logic ones. This allows a power of two to be set for the integration period, for easy normalization in the processor ...
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... Control Word 0, Bit 0 is set to 1, the feedback in the phase accumulator is zeroed when the transfer from the holding to active register occurs. This feature provides 14 HSP50214B synchronization of the phase accumulator starting phase of multiple parts. It can also be used to reset the phase of the NCO synchronous with a specific event. ...
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... Table 1 details the permissible values for the GAINADJ(2:0) barrel shifter control, while Figure 15 shows the permissible CIC Shift Gain values. The CIC filter structure for the HSP50214B is fifth order; that is it has five integrator/comb pairs. A fifth order CIC has 84dB of alias attenuation for output frequencies below 1/8 the CIC output sample rate ...
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... Table 3 assumes that the CIC Shift Gain has been programmed per Equation 7 or 8A. 16 HSP50214B The CIC filter decimation counter can be loaded synchronous with other PDC chips, using the SYNCIN1 signal and the CIC External Sync Enable bit. The CIC external Sync Enable is set via Control Word 0, Bit 19 ...
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... FIGURE 16. CIC FILTER BIT WEIGHTING Since each halfband filter section decimates by 2, the total decimation through the halfband filter is given by: N DEC = 2 HB where N = Number of Halfband Filters Selected (1 - 5). 17 HSP50214B ...
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... NORMALIZED FREQUENCY (F FIGURE 18. HALFBAND FILTER FREQUENCY RESPONSE 0 ALIAS PROFILES -20 -40 -60 HALFBAND FILTER 5 -80 HALFBAND FILTER 4 HALFBAND FILTER 3 HALFBAND FILTER 2 -100 HALFBAND FILTER 1 -120 0.125 0.25 NORMALIZED FREQUENCY (F FIGURE 19. HALFBAND FILTER ALIAS CONSIDERATIONS 18 HSP50214B 0.375 0 -6dB BANDWIDTH 0.375 0 FN4450.4 May 1, 2007 ...
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... HB3 = 1 if this section is selected and bypassed; HB4 = 1 if this section is selected and bypassed; HB5 = 1 if this section is selected and bypassed number of Halfband Filters Selected. The range for T is from HSP50214B TABLE 4. HALFBAND FILTER COEFFICIENTS HALFBAND #2 HALFBAND #3 0.005929947 -0.00130558 ...
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... Figure 20. Note that complex filters can also be realized but are only allowed to be asymmetric. Only the coefficients that are used need to be loaded. 20 HSP50214B C0 EVEN SYMMETRIC EVEN TAP FILTER C0 EVEN SYMMETRIC ...
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... SNR). This effectively eliminates AM spurious caused by the AGC resolution. For fixed gains, either set the upper and lower AGC limits to the same value, or set the limits to minimum and maximum gains and set the AGC loop gain to zero. 21 HSP50214B ...
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... Bits 16-27 are used for programming the upper limit, while bits 0-11 are used to program the lower threshold. The ranges and format for these limit values are shown in Tables 6A through 6C. The bit weightings for the AGC Loop Feedback elements are detailed in Table 9A. 22 HSP50214B ...
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... AGC Slew Rate = 1.5dB THRESH – MAG*1.64676 ( – – ⎛ – ⎝ HSP50214B TABLE 6C. AGC LIMIT DATA FORMAT AGC LOOP FILTER μP (RANGE = -2.18344 TO 2.18344 LIMIT DET AGC LOAD UPPER LIMIT † ...
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... In the HSP50214, a reset event (caused by SYNCIN2 or CW25) would clear the AGC loop filter accumulator. In the ( HSP50214B, if Control Word 27, Bit 15 is set to zero, the AGC loop filter accumulator will clear as in the original HSP50214. If Control Word 27, Bit 15 is set to a one, the (EQ ...
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... FREQUENCY RESPONSE There is a 65dB limitation in SNR using the Re-Sampler Filter. When only the Interpolation FIRs are used, the full SNR range is passed. 25 HSP50214B followed by the 15-tap filter operating at twice the first halfband’s rate. The 23-tap filter requires 7 multiplies, and the 15-tap filter requires 5 multiplies to complete a filter calculation ...
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... AGC Response = 2 ⎝ ⎠ Max 16 15 – 1.64676 ( ) 2 ( AGC Response = 2 Min Thus, the expected range for the AGC rate is ~ 0.000106 to 3.275dB/output sample time. 26 HSP50214B AGC LOOP FILTER GAIN MULTIPLIER SHIFT SHIFT (OUTPUT ...
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... NOTES: 1. SRnd = Symmetric Round; Rnd = Round; SAT = Saturation. 2. The NBW out of the CIC filter is 0 should (9dB or 1.5 bits) versus A/D noise, the processing gain should be 10log(BW 27 HSP50214B TABLE 9B. PDC BIT WEIGHTING CIC BIT CIC IN CIC IN WEIGHTS SHIFT = 0 SHIFT = 15 IIIIICCCCC ...
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... PROCCLK necessary to decimate down to 2x the chip rate to get a realistic number of filter taps. Both interpolation halfband filters are then used to obtain the 8x CDMA output. 944MIPS is a lot of MIPS. The HSP50214B gets the ) S equivalent processing by decimating down and interpolating backup ...
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... Reference clock. Figure 26 details the block diagram of the timing error generation circuit. The 16-bits of timing error are available both as a PDC serial output and as a processor read parameter. See the Processor Read Section for more details on accessing this value. 29 HSP50214B TIMING FILTER PHASE NCO SELECT ACC. ...
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... I and Q. In the HSP50214B, an additional data path option was added that allows the output of the 255 tap programmable π/2 FIR filter to be routed directly to the coordinate converter. ...
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... FIR SYMMETRY TYPE † Controlled via microprocessor interface. FIGURE 29. FREQUENCY DISCRIMINATOR BLOCK DIAGRAM The HSP50214B offers an expanded choice of signals to be filtered by the discriminator FIR. The choices are: 1) 18-bits of delayed, and subtracted (and optionally shifted) phase. This is the Discriminator FIR filter input found in the HSP50214 ...
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... DSP processor or other baseband processing engine. The use of the interrupt signal from the Programmable Down Converter in conjunction with the 32 HSP50214B request strobes from the controller ensures that data is transferred only when both the controller and the Programmable Down Converter are ready. The Buffer RAM ...
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... AOUT, the DATARDY signal will be at the discriminator FIR output (decimated) rate. FIGURE 33. DATARDY WAVEFORMS WHEN f (FREQUENCY) IS SELECTED AS AOUT 33 HSP50214B Note that the BOUT data word may different rate and skewed in time with respect to DATARDY, depending on the type of data selected for output. This is because of the timing relationships defined above, and because the DATARDY is driven by the AOUT signal ...
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... Control Word 19, Bits 25-27 (SEROUTA), and 28-30 (SEROUTB)), the 34 HSP50214B process for identifying the next word is to select a three bit data type identifier which represents the data type to follow the source data type. Program these bits into the Control Word 19 field representing the “ ...
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... SERIAL OUTPUT SYNC POSITION SERIAL OUTPUT CLOCK POLARITY SERIAL OUTPUT SYNC POLARITY † Controlled via microprocessor interface ‡ Polarity is programmable 35 HSP50214B † AGC DATA SERIAL OUTPUT TAG BIT † TIMING ERROR DATA SERIAL OUTPUT TAG BIT † FREQUENCY DATA SERIAL OUTPUT TAG BIT † ...
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... SEROUTB. The choices for the remaining data word in the SEROUTB signal are: phase, frequency, AGC level and timing error. Table 15 illustrates how Control Word 19 should be programmed. 36 HSP50214B TABLE 15. EXAMPLE 2 SERIAL OUTPUT CONTROL SETTINGS CONTROL WORD 19 BIT POSITION 30-28 ...
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... I, Q, magnitude, phase, and frequency data. The RAM samples are mapped as shown in Table 16. The Buffer RAM controller supports both FIFO and Snapshot modes. 37 HSP50214B CONTROL WORD 19, BITS 24-21 = 011 (3 DATA WORDS IN EACH SERIAL OUTPUT) DATA WORD 2 Q DATA WORD 2 MAGNITUDE FIGURE 35 ...
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... New data only read when OEBL goes low, so use μP for 8- bit modes. Programming SEL(2:0) = 110 outputs a 16-bit status signal on AOUT and BOUT. The FIFO status includes FULL, EMPTY, FIFO Depth, and READYB. These status signals are defined in Table 18. 38 HSP50214B ...
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... FIFO must be monitored by the user via a status read. INTRRP OEAL PDC AOUT(7:0) OEBL BOUT(7:0) SEL(2:0) FIGURE 38. INTERFACE BETWEEN A 16-BIT MICROPROCESSOR AND PDC IN FIFO BUFFER 39 HSP50214B INTRRP OEAL, OEBL SEL(0:2) AOUT(7:0), BOUT(7: PROCCLK FIGURE 39. TIMING DIAGRAM FOR PDC IN FIFO MODE WITH OUTPUTS I, Q, AND FREQUENCY SENT TO ...
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... READY FIGURE 40D. FIFO READY IS WHEN (WRITE - READ) > DEPTH FIGURE 40. 40 HSP50214B FIFO Operation Via 8-Bit μProcessor Interface The Buffer RAM Output may also be accessed via the 8-bit microprocessor interface C(7:0). Figure 41 shows the conceptual configuration of the 8-bit μprocessor interface. Control Word 20, Bit 24 must be set order to obtain FIFO Buffer RAM data to this output ...
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... The interval from the start of one snapshot to the start of a second snapshot is programmed into bits 11-4 (where bit 11 is the MSB) of Control Word 21. The actual interval is the 41 HSP50214B |r| ...
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... INTRRP B: FALSE TRIGGERED INTERRUPT READ/WRITE SEQUENCE FIGURE 44. AVOIDING FALSE INTRRP ASSERTIONS 42 HSP50214B Microprocessor Write Section The Microprocessor Write Section uses an indirect addressing scheme where a 32-bit data word is first loaded in a four 8-bit byte master registers using four writes via C(7:0). The desired destination register address is then written to another address using C(7:0) ...
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... Table 22 in the Output Section is sent to C(7:0). This state was provided so that the user could obtain the status bits quickly. Refer to the Timing Diagram in Figure 46. Suppose the input level detector has a hex value of (321AF5)H, then Table 21 details the steps to be taken. 43 HSP50214B PROCLK COMMENT WR RD A2-0 C7-0 ...
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... FDM channel from the FDM band, passing only baseband samples onto the baseband processor at a multiple of the 270.8 KBPS bit rate. 44 HSP50214B 124 CHANNELS FIGURE 47. RECEIVE SIGNAL FREQUENCY SPECTRUM RF/IF Considerations The input frequency to the PDC is dependent on the A/D converter selected, the RF/IF frequency, the bandwidth of interest and the sample rate of the converter ...
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... HSP50210 Data Sheet, Intersil Corporation, FN3652. [2] Cellular Radio and Personal Communications: A Book of Selected Readings, Theodore S. Rappaport, 1995 by IEEE, Inc. [3] AN9720 Application Note, Intersil Corporation, “Calculating Maximum Processing Rates of the PDC (HSP50214B)”. [4] FO-007 Block Diagram of HSP50214. = 541.667kHz S FN4450.4 May 1, 2007 ...
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... CIC INPUT RATE S -130 FREQUENCY FIGURE 48C. HB5 FILTER RESPONSE 10 -10 -30 -50 -70 -90 -110 -130 FIGURE 48. PDC FILTER FREQUENCY SPECTRUMS EXAMPLE (NORMALIZED TO SAME SCALE) 46 HSP50214B 10 -10 -30 -50 -70 -90 -110 f = CIC INPUT RATE S -130 -10 -30 -50 -70 ...
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... Frequency Enable 0 Carrier NCO Load Phase Accum On Update 47 HSP50214B for proper operation of the Microprocessor Write Section. Bits identified as “Reserved” should be programmed to a zero. NOTE: CLKIN or PROCCLK must be present to properly load Reserved. 0- The SYNCIN1 pin has no effect on the Carrier NCO. 1- When the SYNCIN1 pin is asserted, the carrier center frequency and phase are updated from the holding registers to the active register ...
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... CONTROL WORD 3: CARRIER NCO CENTER FREQUENCY (SYNCHRONIZED TO CLKIN) BIT POSITION FUNCTION 31-0 Carrier Center Frequency NOTE: In the HSP50214B, if the SYNCIN1 occurs when the NCO is not updating, the load signal is held internal to the part until the next NCO update. CONTROL WORD 4: CARRIER PHASE OFFSET (SYNCHRONIZED TO CLKIN) BIT POSITION FUNCTION 31-10 ...
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... Selected when AGCGNSEL = 0. These bits are MMMM. See description for bits 15-12. Same equations are used for Loop 0. Bit 7 is the MSB. 3-0 Loop Gain 0 Selected when AGCGNSEL = 0. These bits are EEEE. See description for bits 15-12. Same equations Exponent are used for Loop 0. Bit 3 is the MSB. 49 HSP50214B DESCRIPTION 1001 - 9 1010 - 10 1011 - 11 1100 - 12 1101 - 13 1110 - 14 ...
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... These bits control the frequency of the timing NCO. The frequency range of the NCO is from 0 to Frequency F RESAMP the equation: N =(f loading, a transfer to the Active Register is done by writing to Control Word generating a SYNCIN2 with Control Word 11, Bit 5 set HSP50214B DESCRIPTION GAIN dB/20 ( GAIN dB/20 eeee ...
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... Enabled 100- Not Valid. 101- Not Valid. 110- Both Halfband Filters Enabled. 111- Re-Sampler and Both Halfband Filters Enabled. 51 HSP50214B DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION be delayed from 2 to 255 clocks from the first output. A delay of 2 equals 255 clocks of delay. A delay invalid mode. When interpolating by 2, one extra output is generated; when interpolating extra outputs are generated ...
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... I and one from Q) are related. 20-18 Link Following I Data The serial data word, or link, following the I data word is selected using Table 12 (see Output Section). 52 HSP50214B DESCRIPTION DESCRIPTION DESCRIPTION -(ddd + 1) . FN4450.4 ...
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... Serial Output at PROCCLK/2. 1XX- Serial Output at PROCCLK rate. 13-12 I Data Serial Output 00- No Tag Bit. LSB of word is passed. Tag Bit 01- 0 Tag Bit. LSB of word is set to zero. 1X- 1 Tag Bit. LSB of word is set to one. 53 HSP50214B DESCRIPTION (SYNCHRONIZED WITH PROCCLK) DESCRIPTION 0 1 FN4450.4 May 1, 2007 ...
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... SYNCOUT Strobe A write to this address generates a one clock period wide strobe on the SYNCOUT pin that is synchronized to the clock. This strobe may be synchronized to CLKIN or PROCCLK based on the programming of bit 3 of Control Word 0. 54 HSP50214B (SYNCHRONIZED WITH PROCCLK) (Continued) DESCRIPTION DESCRIPTION 8 ), sample time counts between snapshot samples. Program this ...
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... Reloads shift counter. 2. Reloads “Number of Words” counter. 3. Reloads counter for sync (for early or late). 4. Reloads counter for dividing down SERCLK the HSP50214B, the Control Word 25 reset signal is designed such that the front end reset HSP50214B DESCRIPTION HSP50214B, a configuration control word bit determines if a Timing NCO reset is executed. If Control Word 27, Bit 20 is set to a logic one, a reset will clear the feedback in the timing NCO phase accumulator ...
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... This circuitry must be disabled before loading the coefficient RAM’s. This is done by setting bit 24 to zero. Because the HSP50214 did not require a “write” to Control Word 27 and the HSP50214B does require that Control Word 27, Bit 24 be set to zero for normal operation, software that was written for the HSP50214 will require modification to work properly with the HSP50214B ...
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... The convolution starts with the oldest data, times the last complex coefficient, and ends with the newest data, times the first complex coefficient loaded. Iout Qout = (Xn-k+1_i * Ck-1_im + Xn-k+1_q * Ck-1_re). 57 HSP50214B DESCRIPTION to C are loaded with C in address 64+N, where N is number of asymmetric ...
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... PROCCLK High PROCCLK Low REFCLK Clock Frequency REFCLK High REFCLK Low Setup Time GAINADJ(2:0), IN(13:0), ENI, COF, COFSYNC, and SYNCIN1 to CLKIN 58 HSP50214B Thermal Information Thermal Resistance (Typical, Note 4) +0.5V MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . CC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Pb-free reflow profile ...
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... Controlled via design or process parameters and not directly tested. Characterized upon initial design and at major process or design changes. 9. Setup time required to ensure action initiated by WR will be seen by a particular CLKIN. 59 HSP50214B = 5 ±5 0° to +70°C, Commercial (Note 7); -40°C to +85°C, Industrial (Note 7) (Continued) ...
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... AC Test Load Circuit SWITCH S1 OPEN FOR I NOTE: Test head capacitance. Waveforms t WRL WSA t t WSC C(0-7), A(0-2) FIGURE 49. TIMING RELATIVE 2.0V 0.8V FIGURE 51. OUTPUT RISE AND FALL TIMES 60 HSP50214B S 1 DUT C (NOTE AND I CCSB CCOP EQUIVALENT CIRCUIT RD t WRH A(2-0) WHA WHC C(0- ± ...
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... Waveforms OEAH, OEAL, 1.5V OEBH, OEBL OEBL OUTA(15:8), OUTA(7:0), 1.7V OUTB(15:8), OUTB(7:0) 1.3V FIGURE 53. OUTPUT ENABLE/DISABLE 61 HSP50214B PROCCLK AGCGNSEL, MCSYNC1 SOF, SOFSYNC, SYNCIN2 AOUT(15:0), 1.5V BOUT(15:0), DATARDY, INTRRP, MCSYNC0, t SYNCOUT, SEROUTA, OD SEROUTB SERSYNC FIGURE 54. TIMING RELATIVE TO PROCCLK t RCP f RCP = t RCP Š≥ t RCH t RCL FIGURE 55 ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 62 HSP50214B Q120.28x28 120 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE SYMBOL ...