micrf501 Micrel Semiconductor, micrf501 Datasheet - Page 16

• Manufacturer Part Number: micrf501
• Description: 300mhz To 600mhz Radiowire? Rf Transceiver
• Manufacturer: Micrel Semiconductor

MICRF501
When FSK modulation is applied to the VCO the PLL is using
the dividers A1, N1 and M1. When Mod1 = 1 and Mod0 = 0
it is possible to switch between the different dividers in the
PLL. DATAIXO controls the switching. When DATAIXO = 0
the PLL uses dividers A0, N0 and M0. When DATAIXO = 1 the
PLL uses dividers A1, N1 and M1. Switching between the
different dividers can be used to implement FSK modulation.
The N, M and A values can be calculated from the formula:
where f
The 8bit control word is first read into a shift-register, and is
then loaded into a parallel register by a transition of the
REGIN signal (positive or negative) when the CLKIN signal is
high. The circuit then goes directly into the specified mode
(receive, transmit, etc.).
1. The second last bit is clocked into the first shift register
2. The last bit is clocked into the first shift register (‘1’).
3. A transition on the REGIN signal generates an internal
4. When the clock signal goes low, the power amplifier
5. The power amplifier is fully turned on.
MICRF501
Figure 10. Timing of CLKIN, REGIN and the Internal
(‘1’).
load pulse that loads the control word into the parallel
register. The circuit enters the new mode (in this case
Tx-mode). The circuit stabilizes in the new mode.
(PA) is turned on slowly in order to minimize spurious
components on the RF output signal. To be sure the
PLL is in lock before the PA is turned on, the PA should
be turned on after LOCKDET has been set.
The negative transition on the clock signal should come
a minimum time of one period of the comparison fre-
quency after the internal load pulse is generated.
LOAD_INT
LOCKDET
f
C
REGIN
C
CLKIN
PA_C
=
is the comparison frequency.
f
XCO
M
LOAD_INT and PA_C Signals
1
=
32 N A
× +
2 3
f
RF
4
5
6
7
16
6. A new control word is entered into the first register. A
7. When the power amplifier is turned off an internal load
As long as transitions on REGIN are avoided when CLKIN is
high, a new control word can be clocked into the first register
any time without affecting the operation of the transceiver.
Example 1. f
≈ ±10kHz, f
by switching between dividers.
Binary form: (MSB to the left):
Tx:
Rx:
When FSK modulation is implemented by switching between
the different dividers A, N and M values corresponding to the
receive frequency and both transmit frequencies have to be
found.
transition on the REGIN signal when CLKIN is high will
now turn the power amplifier off.
pulse is generated. The new control word is loaded into
the parallel register and the circuit enters a new mode
(in this case power down mode). CLKIN must go low
after the internal load pulse is generated.
Rx
Rx
Rx
Rx
Rx
Tx
Tx
Tx
Tx
Tx
010010 001011 000001111111
000001110011 0001011110 0001010101
011110000000010010001011
011011 011011 000010001111
000010001111 0001101010 0001101010
011110000000010010001001
OutS1
RxFilt
XCO
Ref6
Ref0
A1
18
27
0
0
0
0
0
0
0
0
RF
= 10.00MHz. FSK modulation is implemented
Cpmp1 Cpmp0
OutS0
= 434.245MHz, frequency deviation:
Ref5
Pa2
A0
11
27
1
1
0
0
1
1
0
0
Mod1
Ref4
Pa1
127
143
N1
1
1
0
0
0
0
1
1
Mod0
Ref3
Pa0
115
143
Fc1
N0
1
1
0
0
0
0
0
0
Ref2
106
Fc0
M1
Gc
RT
94
1
1
0
0
1
1
1
0
March 2003
ByLNA
OutS2
Ref1
106
M0
85
Pu
Micrel
0
0
0
0
0
0
1
1