gal26v12 Lattice Semiconductor Corp., gal26v12 Datasheet - Page 3

• Manufacturer Part Number: gal26v12
• Description: High Performance E2 Cmos Pld Generic Array Logictm Gal26v12 Gal
• Manufacturer: Lattice Semiconductor Corp.

The GAL26V12 has a variable number of product terms per
OLMC. Of the ten available OLMCs, four OLMCs have access
to eight product terms (pins 15, 16, 26 and 27), two have ten prod-
uct terms (pins 17 and 25), two have twelve product terms (pins
18 and 24), two have fourteen product terms (pins 19 and 23), and
two OLMCs have sixteen product terms (pins 20 and 22). In ad-
dition to the product terms available for logic, each OLMC has an
additional product-term dedicated to output enable control.
Each of the Macrocells of the GAL26V12 has two primary func-
tional modes: registered, and combinatorial I/O. The modes and
the output polarity are set by four architecture bits (S0, S1, S2 and
S3), which are normally controlled by the logic compiler. Each
of these two primary modes, and the bit settings required to enable
them, are described below and on the following page.
REGISTERED MODE
In registered mode the output pin associated with an individual
OLMC is driven by the Q output of that OLMC’s D-type flip-flop.
Logic polarity of the output signal at the pin may be selected by
specifying that the output buffer drive either true (active high) or
inverted (active low). Output tri-state control is available as an in-
dividual product-term for each OLMC, and can therefore be de-
fined by a logic equation.
There are two options for the feedback of the registered mode -
- internal /Q feedback and I/O pin feedback. The D flip-flop’s /Q
output is fed back into the AND array, with both the true and com-
plement of the feedback available as inputs to the AND array.
Similarly the I/O pin feedback with both true and complement input
to the AND array. The resulting polarity depends on the input
polarity selection as well as the registered I/O output polarity
configuration.
OUTPUT LOGIC MACROCELL (OLMC)
OUTPUT LOGIC MACROCELL CONFIGURATIONS
GAL26V12 OUTPUT LOGIC MACROCELL (OLMC)
CLK1/
CLK2
2 TO 1
M U X
D
A R
S P
Q
Q
4 T O 1
M U X
3
The output polarity of each OLMC can be individually programmed
to be true or inverting, in either combinatorial or registered mode.
This allows each output to be individually configured as either
active high or active low.
In the registered mode configuration the clock source for the
register can be selected. The two clock options, CLK1 and CLK2,
originate from input pin1 and pin4 respectively.
The GAL26V12 has a product term for Asynchronous Reset (AR)
and a product term for Synchronous Preset (SP). These two
product terms are common to all registered OLMCs. The Asyn-
chronous Reset sets all registers to zero any time this dedicated
product term is asserted. The Synchronous Preset sets all reg-
isters to a logic one on the rising edge of the next clock pulse after
this product term is asserted.
NOTE: The AR and SP product terms will force the Q output of
the flip-flop into the same state regardless of the polarity of the
output. Therefore, a reset operation, which sets the register output
to a zero, may result in either a high or low at the output pin,
depending on the pin polarity chosen.
COMBINATORIAL MODE
In combinatorial mode the pin associated with an individual OLMC
is driven by the output of the sum term gate. Logic polarity of the
output signal at the pin may be selected by specifying that the
output buffer drive either true (active high) or inverted (active low).
Output tri-state control is available as an individual product-term
for each output, and may be individually set by the compiler as
either “on” (dedicated output), “off” (dedicated input), or “product-
term driven” (dynamic I/O).
In combinatorial mode there are also two options for the feedback.
The first feedback option into the AND array is from the I/O pin
side of the output buffer. Both polarities (true and inverted) of the
pin are fed back into the AND array. The second option is to drive
the feedback from /Q of the buried register. This option provides
the combinatorial output with the ability to register the feedback
of the same combinatorial output.
Specifications GAL26V12