ht82m75r Holtek Semiconductor Inc., ht82m75r Datasheet - Page 28

• Manufacturer Part Number: ht82m75r
• Description: I/o Type 8-bit Otp Mcu
• Manufacturer: Holtek Semiconductor Inc.

finally enabled or when a stack level becomes free. The
other situation is where the related interrupt is enabled
and the stack is not full, in which case the regular inter-
rupt response takes place. If an interrupt request flag is
set to 1 before entering the Power Down Mode, the
wake-up function of the related interrupt will be disabled.
No matter what the source of the wake-up event is, once
a wake-up situation occurs, a time period equal to 512
system clock periods will be required before normal sys-
tem operation resumes. However, if the wake-up has
originated due to an interrupt, the actual interrupt sub-
routine execution will be delayed by additional one or
more cycles. If the wake-up results in the execution of
the next instruction following the HALT instruction, this
will be executed immediately after the 512 system clock
period delay has ended.
Watchdog Timer
The Watchdog Timer is provided to prevent program
malfunctions or sequences from jumping to unknown lo-
cations, due to certain uncontrollable external events
such as electrical noise. It operates by providing a de-
vice reset when the WDT counter overflows. The WDT
clock is supplied by its own internal dedicated internal
WDT oscillator. Note that if the WDT configuration op-
tion has been disabled, then any instruction relating to
its operation will result in no operation.
The WDT function is selected by a configuration option.
There is also an internal register associated with the
WDT named WDTS to disable the Watchdog Timer
function and select various WDT time-out periods in the
device. The clock source of the WDT comes from the in-
Rev. 1.10
Watchdog Timer
28
ternal WDT oscillator and its clock period may vary with
VDD, temperature and process variation. The WDT
clock is further divided by an internal 6-stage counter
followed by a 7-stage prescaler to obtain longer WDT
time-out period selected by the WDT prescaler rate se-
lection bits, WS2~WS0, in the associated WDT register
known as WDTS.
There is only one instruction to clear the Watchdog
Timer known as CLR WDT . As the instruction CLR
WDT is executed, all contents of the 6-stage counter
and 7-stage prescaler will be clear. It makes the WDT
time-out period more accurate relatively.
Under normal program operation, a WDT time-out will
initialise a device reset and set the status bit TO. How-
ever, if the system is in the Power Down Mode, when a
WDT time-out occurs, the TO bit in the status register
will be set and only the Program Counter and Stack
Pointer will be reset. Three methods can be adopted to
clear the contents of the WDT. The first is an external
hardware reset, which means a low level on the RES
pin, the second is using the watchdog software instruc-
tions and the third is via a HALT instruction.
Although the WDT overflow is a source to wake up the
MCU from the Power Down Mode, there are some limi-
tations on the conditions at which the WDT overflow oc-
curs. If the WDT function is enabled and the PTR
contents are equal to zeros, the WDT overflow will occur
to wake up the MCU from the Power Down Mode. If the
PTR contents are not equal to zeros, the WDT overflow
will not occur in Power Down Mode even if the WDT
function has been enabled.
HT82M75R/HT82M75RE
HT82K75R/HT82K75RE
June 11, 2010