ht82m75r Holtek Semiconductor Inc., ht82m75r Datasheet
ht82m75r
Related parts for ht82m75r
ht82m75r Summary of contents
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... I/O, mouse/keyboard appliances and SPI con- trol product applications. The advantages of low power consumption, I/O flexibility, Timer functions, Watchdog Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE I/O Type 8-Bit OTP MCU bidirectional I/O lines with pull-high options All I/O pins have falling and rising edge wake-up ...
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... Note: (1) There is an additional peripheral known as the Data EEPROM with capacity of 128 bytes in HT82M75RE and HT82K75RE devices. All information related to the Data EEPROM will be described in the following EEPROM Data Memory section. (2) As devices exist in more than one package format, the table reflects the situation for the package with the most pins ...
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... Pin Assignment Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE 3 June 11, 2010 ...
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... Configuration options determine if the pins have pull-high resistors. Negative power supply, ground Schmitt Trigger reset input. Active low Positive power supply Battery input DC/DC LX switch DC/DC ground +6.0V Storage Temperature ............................ 125 C SS +0.3V Operating Temperature........................... Total............................................................ 100mA OH 4 HT82M75R/HT82M75RE HT82K75R/HT82K75RE June 11, 2010 ...
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... External Reset Low Pulse Width RES t System Start-up Timer SST t Low Voltage Width to Reset LVR t MCU Wake-up Timer Wake-up t Watchdog Time-out Period configure Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE Test Conditions Min. V Conditions DD 1 load 6MHz SYS No load, system HALT WDT disable, LVR disable 0 0.7V ...
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... Parameter I Operating current POR V Rise Rate to Ensure DD RR VDD Power-on Reset Maximum V Start Voltage POR Ensure Power-on Reset Power-on Reset Low Pulse t POR Width Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE Test Conditions Min. V Conditions DD 1.8V~ 3.3V Without 0.1 F between 0.05 V and Without 0.1 F between 0.9 V and V ,Ta= Without 0 ...
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... JMP or CALL that demand a jump to a non-consecutive Program Memory address. It must be noted that only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by user. System Clocking and Pipelining Instruction Fetching 7 HT82M75R/HT82M75RE HT82K75R/HT82K75RE June 11, 2010 ...
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... Program Counter + 2 PC8 @ # S10 Program Counter @7~@0: PCL bits S11~S0: Stack register bits 8 HT82M75R/HT82M75RE HT82K75R/HT82K75RE ...
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... PC11~PC8: Current program counter bits when TBHP is disabled TBHP register bit3~bit0 when TBHP is enabled @7~@0: Table Pointer TBLP bits Rev. 1.10 HT82M75R/HT82M75RE offer users the flexibility to freely develop their applica- tions which may be useful during debug or for products requiring frequent upgrades or program changes. OTP devices are also applicable for use in applications that require low or medium volume production runs ...
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... ISR, the interrupt should be disabled prior to the table read instruction. It Table Read - TBLP only Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE will not be enabled until the TBLH has been backed up. All table related instructions require two cycles to complete the operation. These areas may function as normal program memory depending on the require- ments ...
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... As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation. Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE 11 June 11, 2010 ...
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... The start address of the Data Memory for all devices is the address 00H . Registers which are com- mon to all microcontrollers, such as ACC, PCL, etc., have the same Data Memory address. Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE General Purpose Data Memory All microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later ...
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... Special Purpose Data Memory Structure Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE 13 June 11, 2010 ...
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... Bank 0 while MP1 can access all data banks if the Data Memory is divided into 2 or more banks. ; setup size of block ; setup memory pointer with first RAM address ; clear the data at address defined by MP0 ; increment memory pointer ; check if last memory location has been cleared 14 HT82M75R/HT82M75RE HT82K75R/HT82K75RE June 11, 2010 ...
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... Once TBHP is enabled, the instruction TABRDC [m] reads the ROM data as defined by TBLP and TBHP value. Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE Otherwise, the configuration option TBHP is disabled, the instruction TABRDC [m] reads the ROM data as defined by TBLP and the current program counter bits. ...
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... Data Memory as shown in the Data Memory table, which are used to transfer the appropriate output or in- put data on that port. With each I/O port there is an asso- Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE ciated control register known as PAC, PBC, etc., also mapped to specific addresses with the Data Memory. ...
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... For some pins, the chosen function of the multi-function I/O pins is set by configuration options while for others the function is set by application pro- Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE Input/Output Ports gram control. External Timer Clock Input The external timer pin TMR is pin-shared with the I/O pin PA2 ...
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... An external clock source is used when the timer is in the event counting mode, the clock source being provided on shared pin PA2/TMR. Depending upon the condition Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE of the TE bit, each high to low, or low to high transition on the PA2/TMR pin will increment the counter by one. ...
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... TE or bit 3 of the TMRC register. 16-bit Timer/Event Counter Structure Timer/Event Counter Control Register Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE Configuring the Timer Mode In this mode, the timer can be utilised to measure fixed time intervals, providing an internal interrupt signal each time the counter overflows ...
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... The first is to ensure that the TM0 and TM1 bits place the timer/event counter in the pulse width measuring mode, the second is to en- sure that the port control register configures the pin as an input. Event Counter Mode Timing Chart 20 HT82M75R/HT82M75RE HT82K75R/HT82K75RE June 11, 2010 ...
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... Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE When the Timer/Event Counter is read data is writ- ten to the preload register, the clock is inhibited to avoid errors, however as this may result in a counting error, this should be taken into account by the programmer ...
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... Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE new address which will be the value of the correspond- ing interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector ...
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... By disabling the interrupt enable bit, the requested inter- rupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE condition in the interrupt control register until the corre- sponding interrupt is serviced or until the request flag is cleared by a software instruction ...
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... RES pin remains low for an extended period to allow the power supply to stabilise. During this time delay, normal operation of the microcontroller will be Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE inhibited. After the RES line reaches a certain voltage value, the reset delay time t is invoked to provide ...
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... Characteristics for t details. SST WDT Time-out Reset during Power Down Timing Chart Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the Power Down function or Watchdog Timer ...
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... HT82M75R/HT82M75RE HT82K75R/HT82K75RE RES Reset WDT Time-out (HALT) (HALT)* 000H 000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu ...
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... Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE signer if the power consumption minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be con- ...
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... WDT named WDTS to disable the Watchdog Timer function and select various WDT time-out periods in the device. The clock source of the WDT comes from the in- Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE ternal WDT oscillator and its clock period may vary with VDD, temperature and process variation. The WDT ...
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... Bit No. R/W Name 0~7 Period Timer R/W Rev. 1.10 HT82M75R/HT82M75RE Description 2.2 or 2.0 V Control Register CTLR Description The Period Timer is the time interval generator with one second as a unit. If the bits [7:0] are equal to 00H, the MCU will be woken up by one of the wake-up source mentioned in Wake-up Section except the PTR overflow event ...
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... LVR function or the DC_ctrl bit is set disable the DC/DC circuit, then the LVR function will be dis- abled. If the LVR function is enabled by appropriate set- Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE ting of the configuration option and software control bit as mentioned above, then the LVR still works even if the MCU enters into the Power Down Mode ...
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... SPI mode 7~4 Reserved bit R/W Always 0 Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE The SPIR register is used to select SPI mode, clock po- larity edge selection and SPI enable or disable selec- tion. After Power on, the contents of the SBDR register will unknown condition while the SBCR register will ...
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... TRF data transmitted or received, 0= data is transmitting or still not received CPOL: I/O = clock polarity rising/falling edge: For SPIR Register. If clock polarity set to rising edge (SPI_CPOL=1), serial clock timing follow SCK, otherwise (SPI_CPOL=0) SCK is the serial clock timing. Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE SPI Block Diagram 32 June 11, 2010 ...
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... TXRX buffer until all the data has been received at which point it will be latched into the SBDR register. Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE Step 6. Check the WCOL bit, if set high then a collision error has occurred so return to step5. If equal to zero then go to the following step. ...
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... This bit indicates a data collision has occurred which happens if a write to the SBDR register takes place during a data transfer operation and will prevent the write operation from continuing. The bit will be set high by the Serial Interface but has to be cleared by the Rev. 1.10 HT82M75R/HT82M75RE I/O Status CSEN SPI SCS x ...
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... Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE SPI Bus Timing 35 June 11, 2010 ...
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... Rev. 1.10 SPI Transfer Control Flowchart 36 HT82M75R/HT82M75RE HT82K75R/HT82K75RE June 11, 2010 ...
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... PB0 output type CMOS/NMOS 15 PD pull-high by nibble: pull-high or non-pull-high (*) 16 PE pull-high by nibble: pull-high or non-pull-high (*) 17 PD wake-up by nibble: wake-up or non-wake-up (*) 18 PE wake-up by nibble: wake-up or non-wake-up (*) Note: For HT82K75R, there are additional configuration options as the asterisk marks shown. Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE Options 37 June 11, 2010 ...
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... Application Circuits Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE 38 June 11, 2010 ...
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... An area of EEPROM, which stands for Electrically Eras- able Programmable Read Only Memory, is contained within the device. This type of memory is non-volatile with data retention even after power is removed and is Block Diagram Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE Device Operations: Byte Write Operation Current Address Read Operation Random Address Read Operation ...
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... MCU section. VDDP and VSSP should be externally connected to the MCU power supply named VDD and VSS respectively. The SDA and SCL lines here are internal connected to the MCU I/O pins PC0 and PC1 respectively for these devices. Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE Description 40 June 11, 2010 ...
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... Remark Note Note After this period the first clock pulse is generated Only relevant for repeated START condition Time in which the bus must be free before a new transmission can start Noise suppression time =2.2V to 3.6V 41 HT82M75R/HT82M75RE HT82K75R/HT82K75RE Ta= 40 C~85 C Typ. Max. Unit Ta= 40 C~85 C ...
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... EEPROM. The SDA line is an internal line and not connected to an output pin. Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE Serial clock - SCL The SCL line is the EEPROM serial clock input line which is controlled by the host MCU I/O pin. The host MCU should configure this I/O pin connected to the SCL line as output pin ...
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... ACK will be returned. The master can send the next read/write command when the ACK signal has finally been received. Acknowledge Polling Flow Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE Read operations The data EEPROM supports three read operations, namely, current address read, random address read and sequential read ...
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... Timing Diagrams Note: The write cycle time t is the time from a valid stop condition of a write sequence to the end of the valid start WR condition of sequential command. Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE Current Read Timing Random Read Timing Sequential Read Timing 44 June 11, 2010 ...
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... Application Circuits with EEPROM Data Memory For 32-pin QFN Application Circuit For 48-pin SSOP Application Circuit Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE 45 June 11, 2010 ...
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... Within the Holtek microcontroller instruction set are a range of add and Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to en- sure correct handling of carry and borrow data when re- sults exceed 255 for addition and less than 0 for subtraction ...
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... Increment Data Memory DECA [m] Decrement Data Memory with result in ACC DEC [m] Decrement Data Memory Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the HALT in- struction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electro- magnetic environments ...
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... The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. 4. Configuration option TBHP option is enabled 5. Configuration option TBHP option is disabled Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE Description 48 Cycles Flag Affected 1 ...
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... ACC ACC AND x Affected flag(s) Z ANDM A,[m] Logical AND ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op- eration. The result is stored in the Data Memory. Operation [m] ACC AND [m] Affected flag(s) Z Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE 49 June 11, 2010 ...
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... The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc- tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re- petitively executing this instruction without alternately executing CLR WDT1 will have no effect. Operation WDT cleared TO 0 PDF 0 Affected flag(s) TO, PDF Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE addr 50 June 11, 2010 ...
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... This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. Operation TO 0 PDF 1 Affected flag(s) TO, PDF Rev. 1. HT82M75R/HT82M75RE HT82K75R/HT82K75RE June 11, 2010 ...
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... No operation is performed. Execution continues with the next instruction. Operation No operation Affected flag(s) None OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper- ation. The result is stored in the Accumulator. Operation ACC ACC OR [m] Affected flag(s) Z Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE addr 52 June 11, 2010 ...
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... The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory re- main unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) None Rev. 1.10 Stack Stack Stack [m]. 0~6) 53 HT82M75R/HT82M75RE HT82K75R/HT82K75RE June 11, 2010 ...
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... Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re- places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i [m].(i+1 0~6) ACC [m].0 Affected flag(s) C Rev. 1.10 [m]. 0~6) 54 HT82M75R/HT82M75RE HT82K75R/HT82K75RE June 11, 2010 ...
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... Set Data Memory Description Each bit of the specified Data Memory is set to 1. Operation [m] FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i 1 Affected flag(s) None Rev. 1.10 [ HT82M75R/HT82M75RE HT82K75R/HT82K75RE June 11, 2010 ...
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... The result is stored in the Accumulator. Note that if the result of subtraction is nega- tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ACC Affected flag(s) OV, Z, AC, C Rev. 1.10 0 [m] [ HT82M75R/HT82M75RE HT82K75R/HT82K75RE June 11, 2010 ...
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... If bit i of the specified Data Memory is 0, the following instruction is skipped. As this re- quires the insertion of a dummy instruction while the next instruction is fetched two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Operation Skip if [m]. Affected flag(s) None Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE [m].7 ~ [m].4 [m].7 ~ [m].4 [m].3 ~ [m].0 57 June 11, 2010 ...
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... Operation [m] ACC XOR [m] Affected flag(s) Z XOR A,x Logical XOR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. Operation ACC ACC XOR x Affected flag(s) Z Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE 58 June 11, 2010 ...
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... Symbol Rev. 1.10 Dimensions in inch Min. Nom. 0.228 0.150 0.008 0.335 0.049 0.025 0.004 0.015 0.007 0 Dimensions in mm Min. Nom. 5.79 3.81 0.20 8.51 1.24 0.64 0.10 0.38 0. HT82M75R/HT82M75RE HT82K75R/HT82K75RE Max. 0.244 0.158 0.012 0.347 0.065 0.010 0.050 0.010 8 Max. 6.20 4.01 0.30 8.81 1.65 0.25 1.27 0.25 8 June 11, 2010 ...
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... Symbol Rev. 1.10 Dimensions in inch Min. Nom. 0.228 0.150 0.008 0.386 0.054 0.025 0.004 0.022 0.007 0 Dimensions in mm Min. Nom. 5.79 3.81 0.20 9.80 1.37 0.64 0.10 0.56 0. HT82M75R/HT82M75RE HT82K75R/HT82K75RE Max. 0.244 0.157 0.012 0.394 0.060 0.010 0.028 0.010 8 Max. 6.20 3.99 0.30 10.01 1.52 0.25 0.71 0.25 8 June 11, 2010 ...
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... Symbol Rev. 1.10 Dimensions in inch Min. Nom. 0.028 0.000 0.008 0.007 0.197 0.197 0.020 0.049 0.049 0.012 Dimensions in mm Min. Nom. 0.70 0.00 0.20 0.18 5.00 5.00 0.50 1.25 1.25 0.30 61 HT82M75R/HT82M75RE HT82K75R/HT82K75RE Max. 0.031 0.002 0.012 0.128 0.128 0.020 Max. 0.80 0.05 0.30 3.25 3.25 0.50 June 11, 2010 ...
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... Symbol Rev. 1.10 Dimensions in inch Min. Nom. 0.395 0.291 0.008 0.613 0.085 0.025 0.004 0.025 0.004 0 Dimensions in mm Min. Nom. 10.03 7.39 0.20 15.57 2.16 0.64 0.10 0.64 0. HT82M75R/HT82M75RE HT82K75R/HT82K75RE Max. 0.420 0.299 0.012 0.637 0.099 0.010 0.035 0.012 8 Max. 10.67 7.59 0.30 16.18 2.51 0.25 0.89 0.30 8 June 11, 2010 ...
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... Key Slit Width T1 Space Between Flange T2 Reel Thickness SSOP 48W Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE Dimensions in mm 330.0 1.0 100.0 1.5 +0.5/-0.2 13.0 2.0 0.5 +0.3/-0.2 16.8 22.2 0.2 Dimensions in mm 330.0 1.0 100.0 1.5 +0.5/-0.2 13.0 2.0 0.5 +0.3/-0.2 16.8 22.2 0.2 Dimensions in mm 330 ...
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... Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE Dimensions in mm +0.3/-0.1 16.0 8.0 0.1 1.75 0.10 7.5 0.1 +0.1/-0.0 1.5 +0.25/-0.00 1.50 4.0 0.1 2.0 0.1 6.5 0.1 9.0 0.1 2.3 0.1 0.30 0.05 13.3 0.1 Dimensions in mm 16.0 0.3 8.0 0.1 1.75 0.1 7.5 0.1 +0.10/-0.00 1.55 +0 ...
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... Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K1 Cavity Depth K2 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE Dimensions in mm 32.0 0.3 16.0 0.1 1.75 0.10 14.2 0.1 2 Min. +0.25/-0.00 1.50 4.0 0.1 2.0 0.1 12.0 0.1 16.2 0.1 2.4 0.1 3.2 0.1 0.35 0.05 25.5 0.1 65 June 11, 2010 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.10 HT82M75R/HT82M75RE HT82K75R/HT82K75RE 66 June 11, 2010 ...