wm9703 ETC-unknow, wm9703 Datasheet - Page 21

• Manufacturer Part Number: wm9703
• Manufacturer: ETC-unknow

Production Data
SERIAL INTERFACE REGISTER MAP DESCRIPTION
WOLFSON MICROELECTRONICS LTD
Once powered down, re-activation of the AC-link via re-assertion of the SYNC signal must not occur
for a minimum of 4 audio frame times following the frame in which the powerdown was triggered.
When AC-link powers up it indicates readiness via the Codec Ready bit (input slot 0, bit 15).
COLD WM9703 RESET
A cold reset is achieved by asserting RESETB for the minimum specified time. By driving RESETB
low, BIT_CLK, and SDATA_OUT will be activated, or re-activated as the case may be, and all the
WM9703 control registers will be initialised to their default power on reset values.
RESETB is an asynchronous WM9703 input.
WARM WM9703 RESET
A warm WM9703 reset will re-activate the AC-link without altering the current WM9703 register
values. A warm reset is signalled by driving SYNC high for a minimum of 1 S in the absence of
BIT_CLK.
Within normal audio frames SYNC is a synchronous input. In the absence of BIT_CLK, SYNC is
treated as an asynchronous input used in the generation of a warm reset to the WM9703. The
WM9703 will not respond with the activation of BIT_CLK until SYNC has been sampled low again by
the WM9703. This will preclude the false detection of a new audio frame.
(See Table 21)
The serial interface bits perform control functions described as follows: The register map is fully
specified by the AC’97 specification, and this description is simply repeated below, with optional
unsupported features omitted.
RESET REGISTER (INDEX 00h)
Writing any value to this register performs a register reset, which causes all registers to revert to their
default values. Reading this register returns the ID code of the part, indication of modem support (not
supported by the WM9703) and a code for the type of 3D stereo enhancement.
The ID decodes the capabilities of the WM9703 based on the following:
Table 9 Reset Register Function
Note that the WM9703 defaults to indicate 18-bit compatibility. However, a control bit may be set in
the vendor-specific registers that changes bits ID6 and ID8 to be 0, indicating a 16-bit device. It is
unlikely that this function will be required, however, as the MSB justification of the ADC and DAC
data means that a nominally 18-bit device should be fully compatible with controllers that only
provide 16-bit support. Most PC type applications will only require 16-bit operation.
PLAY MASTER VOLUME REGISTERS (INDEX 02h, 04h AND 06h)
These registers manage the output signal volumes. Register 02h controls the stereo master volume
(both right and left channels), Register 04h controls the optional stereo headphone out, and Register
06h controls the mono volume output. Each step corresponds to 1.5dB. The MSB of the register is
the mute bit. When this bit is set to 1 the level for that channel is set at -
ML5 to ML0 is for left channel level, MR5 to MR0 is for the right channel and MM5 to MM0 is for the
mono out channel.
SE4...SE0
ID0
ID1
ID2
ID3
ID4
ID5
ID6
ID7
ID8
ID9
BIT
FUNCTION
Dedicated Mic PCM in channel
Modem line codec support
Bass and treble control
Simulated stereo (mono to stereo)
Headphone out support
Loudness (bass boost) support
18-bit DAC resolution
20-bit DAC resolution
18-bit ADC resolution
20-bit ADC resolution
Wolfson Microelectronics 3D enhancement
dB.
PD Rev 3.4 January 2001
VALUE ON
WM9703
11000
WM9703
0
0
0
0
1
0
1
0
1
0
21