wm9090 Wolfson Microelectronics plc, wm9090 Datasheet - Page 33

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wm9090

Manufacturer Part Number
wm9090
Description
Ultra Low Power Audio Subsystem
Manufacturer
Wolfson Microelectronics plc
Datasheet
w
Pre-Production
Figure 8 Control Interface Register Write
Figure 9 Control Interface Register Read
SCLK
SDA
START
D7
device ID
D1
(Write)
R/W
ACK
The sequence of signals associated with a single register write operation is illustrated in Figure 8.
The sequence of signals associated with a single register read operation is illustrated in Figure 9.
The Control Interface also supports other register operations, as listed above. The interface protocol
for these operations is summarised below. The terminology used in the following figures is detailed in
Table 18.
Note that multiple write and multiple read operations are supported using the auto-increment mode.
This feature enables the host processor to access sequential blocks of the data in the WM9090
register map faster than is possible with single register operations.
Table 18 Control Interface Terminology
Note: The SDA pin is driven by both the master and slave devices in turn to transfer device address, register address, data and ACK responses
A7
register address
TERMINOLOGY
[White field]
[Grey field]
A1
R/W ¯ ¯
A ¯ ¯
Sr
S
A
P
A0
ACK
START
Rpt
D6
device ID
ReadNotWrite
Data flow from bus master to WM9090
Data flow from WM9090 to bus master
D0
(Read)
Not Acknowledge (SDA High)
R/W
Acknowledge (SDA Low)
ACK
Start Condition
DESCRIPTION
Repeated start
Stop Condition
B15
data bits B15 – B8
B9
B8
0 = Write
1 = Read
ACK
B7
PP, January 2010, Rev 3.0
data bits B15 – B8
B1
B0
WM9090
ACK
STOP
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