xr16l2751im Exar Corporation, xr16l2751im Datasheet - Page 31

• Manufacturer Part Number: xr16l2751im
• Description: 2.25v To 5.5v Duart With 64-byte Fifo And Powersave
• Manufacturer: Exar Corporation

xr
REV. 1.2.2
LCR[6]: Transmit Break Enable
When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a
“space", LOW state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.
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LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL/DLM) enable.
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The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Output
The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
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MCR[1]: RTS# Output
The RTS# pin is a modem control output and may be used for automatic hardware flow control by enabled by
EFR bit-6 or auto RS-485 half-duplex direction control output enabled by FCTR bit-3. If the modem interface is
not used, this output may be used as a general purpose output.
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MCR[2]: Reserved
OP1# is not available as an output pin on the 2751. But it is available for use during Internal Loopback Mode.
In the Loopback Mode, this bit is used to write the state of the modem RI# interface signal.
MCR[3]: OP2# Output / INT Output Enable
This bit enables and disables the operation of INT/IRQ#, interrupt output. If INT/IRQ# output is not used, OP2#
can be used as a general purpose output. Also, if 16/68# pin selects Motorola bus interface mode, this bit must
be set to logic 0.
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MCR[4]: Internal Loopback Enable
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MCR[5]: Xon-Any Enable
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4.7
Logic 0 = No TX break condition. (default)
Logic 1 = Forces the transmitter output (TX) to a “space”, LOW, for alerting the remote receiver of a line
break condition.
Logic 0 = Data registers are selected. (default)
Logic 1 = Divisor latch registers are selected.
Logic 0 = Force DTR# output HIGH (default).
Logic 1 = Force DTR# output LOW.
Logic 0 = Force RTS# output HIGH (default).
Logic 1 = Force RTS# output LOW.
Logic 0 = INT (A-B) outputs disabled (three state mode) and OP2# output set HIGH (default).
Logic 1 = INT (A-B) outputs enabled (active mode) and OP2# output set LOW.
Logic 0 = Disable loopback mode (default).
Logic 1 = Enable local loopback mode, see loopback section and
Logic 0 = Disable Xon-Any function (for 16C550 compatibility, default).
Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation.
The RX character will be loaded into the RX FIFO, unless the RX character is an Xon or Xoff character and
the 2751 is programmed to use the Xon/Xoff flow control.
Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
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Figure
13.
XR16L2751