xr16l2751im Exar Corporation, xr16l2751im Datasheet - Page 12

• Manufacturer Part Number: xr16l2751im
• Description: 2.25v To 5.5v Duart With 64-byte Fifo And Powersave
• Manufacturer: Exar Corporation

XR16L2751
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
Each UART has its own Baud Rate Generator (BRG) with a prescaler. The prescaler is controlled by CLKSEL
hardware pin or a software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide the input
crystal or external clock by 1 or 4 and can override the CLKSEL pin following reset. The clock output of the
prescaler goes to the BRG. The BRG further divides this clock by a programmable divisor between 1 and (2
1) to obtain a 16X sampling rate clock of the serial data rate. The sampling rate clock is used by the transmitter
for data bit shifting and receiver for data sampling. The BRG divisor defaults to the maximum baud rate (DLL =
0x01 and DLM = 0x00) upon power up.
Programming the Baud Rate Generator Registers DLM and DLL provides the capability of selecting the
operating data rate.
clock at 16X sampling rate clock rate. A 16X sampling clock is typically used. However, user can select the 8X
sampling clock rate mode (EMSR bit-7=0) to double the operating data rate. When using a non-standard data
rate crystal or external clock, the divisor value can be calculated for DLL/DLM with the following equation.
2.10
O
UTPUT
MCR Bit-7=1
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16), with 16XMode [EMSR bit-7] = 1
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 8), with 16XMode [EMSR bit-7] = 0
230.4k
115.2k
19.2k
38.4k
57.6k
1200
2400
4800
9600
100
600
Data Rate
Programmable Baud Rate Generator
F
T
IGURE
ABLE
XTAL1
XTAL2
O
UTPUT
Table 6
6. B
6: T
MCR Bit-7=0
(
DEFAULT
153.6k
230.4k
460.8k
921.6k
19.2k
38.4k
76.8k
YPICAL DATA RATES WITH A
2400
4800
9600
AUD
400
Data Rate
shows the standard data rates available with a 14.7456 MHz crystal or external
R
Crystal
Buffer
)
Osc/
ATE
G
Clock (Decimal)
D
ENERATOR AND
IVISOR FOR
2304
384
192
96
48
24
12
6
4
2
1
Divide by 4
Divide by 1
Prescaler
Prescaler
16x
14.7456 MH
P
D
12
RESCALER
IVISOR FOR
Clock (HEX)
MCR Bit-7=0
MCR Bit-7=1
(default)
900
180
C0
0C
60
30
18
06
04
02
01
Z CRYSTAL OR EXTERNAL CLOCK
16x
Baud Rate
DLL and DLM
Generator
Registers
Logic
V
ALUE
P
ROGRAM
DLM
09
01
00
00
00
00
00
00
00
00
00
(HEX)
Rate Clock to
Transmitter
Sampling
V
16X
ALUE
P
ROGRAM
DLL
C0
0C
00
80
60
30
18
06
04
02
01
(HEX)
xr
D
E
REV. 1.2.2
ATA
RROR
0
0
0
0
0
0
0
0
0
0
0
R
ATE
(%)
16
-