ak5392 AKM Semiconductor, Inc., ak5392 Datasheet - Page 8

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ak5392

Manufacturer Part Number
ak5392
Description
Enhanced Dual Bit ?? 24bit Adc
Manufacturer
AKM Semiconductor, Inc.
Datasheet

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ASAHI KASEI
0188-E-01
Notes: 9 . Refer to Serial Data interface.
Control Clock Frequency
Serial Interface Timing
Reset/Calibration timing
(Ta=25
Master Clock
Serial Data Output Clock (SCLK)
Channel Select Clock (LRCK)
Slave Mode(SMODE1="L")
Master Mode(SMODE1="H")
RST
RST
RST
RST
SCLK Period
SCLK Pulse Width Low
SCLK falling to LRCK Edge (Note 10 )
LRCK Edge to SDATA MSB Valid
SCLK falling to SDATA Valid
SCLK falling to FSYNC Edge
SCLK Frequency
FSYNC Frequency
SCLK falling to LRCK Edge
LRCK Edge to FSYNC rising
SCLK falling to SDATA Valid
SCLK falling to FSYNC Edge
10 . Specified LRCK edges not to coincide with the rising edges of SCLK.
11 . The number of the LRCK rising edges after
duty cycle
Pulse width High
duty cycle
Pulse width
falling to CAL rising
rising to CAL falling
rising to SDATA Valid
C
In slave mode it becomes one LRCK clock(1/fs) longer.
duty cycle
; VA=5.0V±5%; VD=3.0 5.25V; CL=20pF)
384fs:
256fs:
Parameter
Pulse width Low
Pulse width High
Pulse width Low
Pulse width High
(Note 11 )
(Note 11 )
(Note 9 )
SWITCHING CHARACTERISTICS
RST
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fSLK
fs
tSLK
tSLKL
tSLKH
tSLR
tDLR
tDSS
tSF
fSLK
fFSYNC
tSLR
tLRF
tDSS
tSF
tRTW
tRCR
tRCF
tRTV
- 8 -
Symbol
brought high. The value is in master mode.
0.256
0.384
144.7
Min
150
-45
-45
-20
-20
29
29
20
20
25
65
65
1
12.288
18.432
6.144
128fs
8704
8960
Typ
2fs
48
50
50
1
13.824
20.736
6.912
Max
54
75
45
45
45
45
20
45
20
50
[AK5392]
1997/11
Units
MHz
MHz
MHz
kHz
tslk
1/fs
1/fs
Hz
Hz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
%
%

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