ak5392 AKM Semiconductor, Inc., ak5392 Datasheet - Page 4

• Manufacturer Part Number: ak5392
• Description: Enhanced Dual Bit ?? 24bit Adc
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
0188-E-01
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TEST
VA
VCOMR
VREFR
SCLK
SDATA
FSYNC
CLK
CMODE
HPFE
BGND
AGND
AINR-
AINR+
GNDR
I/O
I/O
O
O
O
I
I
I
I
-
-
-
I
I
-
Test Pin
Serial Data Clock Pin
Serial Data Output Pin
Frame Synchronization Signal Pin
Master Clock Input Pin
Master Clock Select Pin
High Pass Filter Enable Pin
Substrate Ground Pin, 0V
Analog Ground Pin, 0V
Analog Supply Pin, 5V
Rch Analog negative input Pin
Rch Analog positive input Pin
Rch Common Voltage Pin, 2.5V
Rch Reference Ground Pin, 0V
Rch Reference Voltage Pin, 3.75V
Data is clocked out on the falling edge of SCLK.
Slave mode:
Master mode:
MSB first, 2's complement. SDATA stays "L" during reset.
Slave mode:
Master mode:
CMODE="H":384fs
CMODE="L":256fs
"L": CLK=256fs (12.288MHz @fs=48kHz)
"H": CLK=384fs (18.432MHz @fs=48kHz)
"L": Disable
"H": Enable
Should be connected DGND.
Normally connected to GNDR with a 10uF electrolytic capacitor and
a 0.1uF ceramic capacitor
SCLK outputs a 128fs clock. SCLK stays "L" during reset.
SCLK requires more than 48fs clock.
FSYNC outputs 2fs clock.
FSYNC stays "L" during reset.
When "H", the data bits are clocked out on SDATA.
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[AK5392]
1997/11