ak5394a AKM Semiconductor, Inc., ak5394a Datasheet - Page 5

• Manufacturer Part Number: ak5394a
• Description: Super High Performance 192khz 24-bit ?? Adc
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
Note: All digital inputs should not be left floating.
MS0137-E-03
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SCLK
SDATA
FSYNC
MCLK
DFS0
HPFE
DFS1
BGND
AGND
VA
AINR−
AINR+
VCOMR
VREFR−
VREFR+
I/O
I/O
O
O
O
O
I
I
I
I
-
-
-
I
I
Serial Data Clock Pin
Serial Data Output Pin
Frame Synchronization Signal Pin
Master Clock Input Pin
Sampling Speed Select Pin 0
High Pass Filter Enable Pin
Sampling Speed Select Pin 1
Substrate Ground Pin, 0V
Analog Ground Pin, 0V
Analog Supply Pin, 5V
Rch Analog negative input Pin
Rch Analog positive input Pin
Rch Common Voltage Pin, 2.75V
Rch Negative Reference Voltage, 1.25V
Rch Positive Reference Voltage, 3.75V
MSB first, 2’s complement.
(see #18 DFS0)
SDATA is clocked out on the falling edge of SCLK.
Slave mode:
Master mode:
Slave mode:
Master mode:
“L”: Disable
“H”: Enable
Normally connected to AGND with a large electrolytic capacitor and connected
to VREFR+ with a 0.22µF ceramic capacitor.
Normally connected to AGND with a large electrolytic capacitor and connected
to VREFR- with a 0.22µF ceramic capacitor.
DFS1
DFS1
don’t care.
AK5394A outputs following clocks as SCLK.
When RSTN pin = “L”, SCLK outputs “L”(normal/double speed mode) or
outputs the inverted MCLK (quad speed mode).
SCLK requires more than 48fs clock.
When “H”, the data bits are clocked out on SDATA. In I
FSYNC outputs 2fs clock.
FSYNC stays “L” during reset.
L
L
H
H
L
L
H
H
Normal Speed Mode: 128fs
Double Speed Mode: 64fs
Quad Speed Mode: 64fs
DFS0
DFS0
L
H
L
H
L
H
L
H
- 5 -
MCLK
256fs
128fs
192kHz
(N/A)
64fs
48kHz
96kHz
(N/A)
fs(typ)
192kHz
48kHz
96kHz
fs(typ)
(N/A)
2
S mode, FSYNC is
[AK5394A]
2005/05