ak5367 AKM Semiconductor, Inc., ak5367 Datasheet - Page 14

• Manufacturer Part Number: ak5367
• Description: 96khz 24-bit Adc With 0v Bias Selector
• Manufacturer: AKM Semiconductor, Inc.

L
MCLK, BICK and LRCK clocks are required. The LRCK clock input must be synchronized with MCLK, however the
phase is not critical.
MCLK, BICK and master/slave mode setting are selected by CKS2-0
In slave mode, all external clocks (MCLK, BICK and LRCK) must be present unless PDN pin = “L”. If these clocks are
not provided, the AK5367 may draw excess current due to its use of internal dynamically refreshed logic. If the external
clocks are not present, place the AK5367 in power-down mode (PDN pin = “L”). In master mode, the master clock
(MCLK) must be provided unless PDN pin = “L”. It is not necessary to reset by bringing PDN pin “L” when clocks and
fs are changed. They should be changed after soft mute (SMUTE bit = “1”) to avoids the switching noise.
Note 18. The SDTO output is 16bit when BICK=32fs input.
MS0694-E-00
System Clock
Mode
0
1
2
3
4
5
6
7
CKS2
0
0
0
0
1
1
1
1
44.1kHz
Table 1
32kHz
48kHz
96kHz
CKS1
fs
0
0
1
1
0
0
1
1
shows the relationship of typical sampling frequency and the system clock frequency. The
Table 1. System Clock Example (N/A: Not available)
CKS0
11.2896MHz
12.288MHz
24.576MHz
8.192MHz
0
1
0
1
0
1
0
1
256fs
Master/Slave
Table 2. Operation Mode Select
OPERATION OVERVIEW
Master
Master
Master
Master
Slave
16.9344MHz
12.288MHz
18.432MHz
36.864MHz
384fs
- 14 -
256/384fs (32k fs 96k)
512/768fs (32k fs 48k)
MCLK
256fs (32k fs 96k)
512fs (32k fs 48k)
384fs (32k fs 96k)
768fs (32k fs 48k)
22.5792MHz
Reserved
Reserved
Reserved
16.384MHz
24.576MHz
bits(Table
MCLK
512fs
N/A
2).
33.8688MHz
24.576MHz
36.864MHz
768fs
N/A
48fs or 32fs
(Note
BICK
64fs
64fs
64fs
64fs
18)
(default)
[AK5367]
2007/12