ak5702 AKM Semiconductor, Inc., ak5702 Datasheet - Page 24

• Manufacturer Part Number: ak5702
• Description: 4-channel Adc With Pll & Mic-amp
• Manufacturer: AKM Semiconductor, Inc.

When PLL reference clock input is LRCK or BCLK pin, the sampling frequency is selected by FS3 and FS2 bits (Table
6).
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1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
In this mode, LRCK and BCLK pins go to “L” and irregular frequency clock is output from MCKO pins at MCKO bit is
“1” before the PLL goes to lock state after PMPLL bit = “0” → “1”. If MCKO bit is “0”, MCKO pin goes to “L” (Table
7).
In DSP Mode 0, BCLK and LRCK start to output corresponding to Lch data after PLL goes to lock state by setting
PMPLL bit = “0” → “1”. When MSBS bit = “0” and BCKP bit = “1” or MSBS bit = “1” and BCKP bit = “0” in DSP Mode
0, BCLK “H” time of the first pulse becomes shorter by 1/(256fs) than “H” time except for the first pulse.
When sampling frequency is changed, BCLK and LRCK pins do not output irregular frequency clocks but go to “L” by
setting PMPLL bit to “0”.
2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
In this mode, an invalid clock is output from MCKO pin before the PLL goes to lock state after PMPLL bit = “0” → “1”.
After that, the clock selected by Table 9 is output from MCKO pin when PLL is locked. The ADC output invalid data
when the PLL is unlocked.
MS0623-E-00
PLL State
After that PMPLL bit “0” → “1”
PLL Unlock (except above case)
PLL Lock
PLL Unlock State
Others
Mode
0
1
2
Table 6. Setting of Sampling Frequency at PMPLL bit = “1” and Reference=LRCK/BCLK
Table 7. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
FS3 bit
Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
0
0
1
PLL State
After that PMPLL bit “0” → “1”
PLL Unlock (except above case)
PLL Lock
Don’t care
FS2 bit
0
1
MCKO bit = “0”
Others
“L” Output
“L” Output
“L” Output
Don’t care
Don’t care
Don’t care
FS1 bit
MCKO pin
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MCKO bit = “0”
Don’t care
Don’t care
Don’t care
FS0 bit
“L” Output
“L” Output
“L” Output
MCKO bit = “1”
See Table 9
Invalid
Invalid
MCKO pin
Sampling Frequency
12kHz < fs ≤ 24kHz
24kHz < fs ≤ 48kHz
7.35kHz ≤ fs ≤ 12kHz
MCKO bit = “1”
See Table 9
Invalid
Invalid
See Table 10
Range
“L” Output
N/A
BCLK pin
Invalid
“L” Output
1fs Output
LRCK pin
(default)
Invalid
[AK5702]
2007/06