ak5702 AKM Semiconductor, Inc., ak5702 Datasheet
ak5702
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ak5702 Summary of contents
Page 1
... The AK5702 features a 4-channel ADC. Input circuits include a Microphone-Amplifier with programmable gain and an ALC (Auto Level Control) circuit, making it ideal for consumer microphone array applications. On-chip PLL and TDM audio format makes it easy to connect with DSP. The AK5702 has a software compatibility with stereo version, AK5701. ...
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... VCOM AVDD VSS1 VCOC PLL MCKO MCKI MS0623-E-00 ALC or ADCA HPF MIX IVOL ALC ADCB or HPF MIX IVOL Control Register TEST CAD0 CSN CCLK CDTI Figure 1. Block Diagram - 2 - [AK5702] LRCK BCLK Audio I/F SDTOA Controller SDTOB TDMIN DVDD VSS2 PDN I2C 2007/06 ...
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... Comparison with AK5701 Function # of ADC channel Input Selector Cascade TDM interface Bypass mode uP I/F Package MS0623-E-00 −30 ∼ +85°C 32pin QFN (0.5mm pitch) Evaluation board for AK5702 AK5702VN Top View AK5701 2 2 stereo No Yes 3-wire 24pin QFN (4mm x 4mm [AK5702] CSN ...
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... Lch Positive Input B Pin (MDIFB2 bit = “1”: Full-differential Input) Rch Analog Input 3 Pin (MDIFB2 bit = “0”: Single-ended Input) Lch Negative Input B Pin (MDIFB2 bit = “1”: Full-differential Input Function 2 C Bus Mode Bus Mode Bus Mode) [AK5702] 2007/06 ...
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... These pins should be open. These pins should be open. This pin should be connected to VSS2. ABSOLUTE MAXIMUM RATINGS Symbol AVDD DVDD IIN VINA VIND Ta Tstg Symbol min AVDD 2.4 DVDD 1.6 2.0 2 [AK5702] min max −0.3 4.6 −0.3 4.6 ±10 - −0.3 AVDD+0.3 −0.3 DVDD+0.3 −30 85 −65 150 typ max 3.0 3.6 3 ...
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... MGAIN=+36dB - MGAIN=+30dB - MGAIN=+15dB - MGAIN=0dB - 2.02 0.5 - MGAIN=+15dB, IVOL=0dB, ALC=OFF - MGAIN=+36dB - MGAIN=+30dB - MGAIN=+15dB 0.27 MGAIN=0dB 1. MGAIN=+36dB - MGAIN=+30dB - MGAIN=+15dB - MGAIN=0dB - - 6 - [AK5702] typ max Units +15 - + 0.033 Vpp - 0.066 Vpp - 0.37 Vpp - 2.07 Vpp 2.25 2.48 - ...
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... VIL VIL VOH DVDD−0.2 (Iout= 200μA) VOL VOL VOL Iin - 7 - typ max - 17.4 20 ±0 3 min typ max - - - - - - 30%DVDD - - 20%DVDD - - - - 0 0 20%DVDD ± [AK5702] Units kHz kHz kHz kHz dB dB 1/fs μ Units μA 2007/06 ...
Page 8
... Duty 45 tLRCKH - tLRCKH - tBCK 1/(64fs) tBCK 1/(64fs) tBCK - tBCK - tBCKL 0.4 x tBCK tBCKH 0.4 x tBCK - 8 - [AK5702] typ max Units - 27 MHz - - 12.288 MHz kHz tBCK - 1/(8fs 1/(8fs) ...
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... Duty 45 - tLRCKH - 1/(128fs) tLRCKH - 1/(256fs) tBCK 312.5 - tBCK 78 - tBCKL 130 - tBCKL 32 - tBCKH 130 - tBCKH [AK5702] max Units 48 kHz 1/fs − tBCK 1/(32fs kHz 1/fs − tBCK 12.288 MHz 13.312 MHz 13.312 MHz ...
Page 10
... Duty - 50 tLRCKH - 1/(8fs) tLRCKH - 1/(8fs) tBCK - 1/(32fs) tBCK - 1/(64fs) tBCK - 1/(128fs) tBCK - 1/(256fs) dBCK - [AK5702] max Units 12.288 MHz 13.312 MHz 13.312 MHz - kHz - 2007/06 ...
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... Units 0.5 x tBCK 0.5 x tBCK + 40 0.5 x tBCK 0.5 x tBCK + ...
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... registered trademark of Philips Semiconductors. Note 24. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. Note 25. The AK5702 can be reset by the PDN pin = “L”. Note 26. This is the count of LRCK “↑” from the PMADAL, PMADAR, PMADBL, PMADBR bit = “1”. ...
Page 13
... Duty = tLRCKH 100 tBCK tBCKH tBCKL dBCK = tBCKH / tBCK x 100 1/fMCK tMCKL dMCK = tMCKL x fMCK x 100 Figure 2. Clock Timing (PLL/EXT Master mode) tMBLR tLRD - 13 - VIH VIL 50%DVDD tLRCKL 100 50%DVDD tBCKL / tBCK x 100 50%DVDD 50%DVDD tBCKL 50%DVDD tBSD 50%DVDD [AK5702] 2007/06 ...
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... BCLK (BCKP = "0") SDTO Figure 5. Audio Interface Timing (PLL/EXT Master mode & DSP mode: MSBS = “1”) MS0623-E-00 tLRCKH tBCK tDBF dBCK tBSD MSB tLRCKH tBCK tDBF dBCK tBSD - 14 - [AK5702] 50%DVDD 50%DVDD 50%DVDD 50%DVDD 50%DVDD 50%DVDD 50%DVDD MSB 50%DVDD 2007/06 ...
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... LRCK BCLK SDTO TDMIN Figure 6. Audio Interface Timing (PLL/EXT Master mode & TDM mode) MS0623-E-00 tMBLR tBSD tTDMS tTDMH - 15 - 50%DVDD dBCK 50%DVDD 50%DVDD VIH VIL [AK5702] 2007/06 ...
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... Figure 8. Clock Timing (PLL Slave mode; PLL Reference Clock = LRCK or BCLK pin & DSP mode; MSBS = 1) MS0623-E-00 1/ tBCK tBCKH tBCKL 1/ tBCK tBCKH tBCKL - 16 - [AK5702] VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH ...
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... Duty = tLRCKH 100 tBCK tBCKH tBCKL fMCK tMCKL dMCK = tMCKL x fMCK x 100 tLRCKH tLRB tBSD MSB - 17 - VIH VIL VIH VIL = tLRCKL 100 VIH VIL 50%DVDD VIH VIL VIH VIL VIH VIL 50%DVDD [AK5702] 2007/06 ...
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... MS0623-E-00 tLRCKH tLRB tBSD 1/fCLK tCLKH tCLKL 1/fs Duty = tLRCKH 100 tLRCKH tLRCKL tBCK tBCKH tBCKL Figure 12. Clock Timing (EXT Slave mode [AK5702] VIH VIL VIH VIL VIH VIL 50%DVDD MSB VIH VIL VIH VIL tLRCKL 100 VIH VIL 2007/06 ...
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... Figure 13. Audio Interface Timing (PLL/EXT Slave mode) LRCK tBLR BCLK SDTO TDMIN Figure 14. Audio Interface Timing (PLL/EXT Slave mode & TDM mode) MS0623-E-00 tLRB tLRD tBSD MSB tLRB tBSD tTDMS tTDMH - 19 - [AK5702] VIH VIL VIH VIL 50%DVDD VIH VIL VIH VIL 50%DVDD VIH VIL 2007/06 ...
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... Figure 16. WRITE Data Input Timing tHIGH tR tF tHD:DAT tSU:DAT tSU:STA Start 2 Figure 17. I CBUS Timing - 20 - tCCKH tCCK tCDH C0 R/W tCSW tCSH tCSS D0 tSP tSU:STO [AK5702] VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL Stop 2007/06 ...
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... PMADAL bit or PMADAR bit or PMADBL bit or PMADBR bit SDTO PDN MS0623-E-00 tPDV Figure 18. Power Down & Reset Timing 1 tPD Figure 19. Power Down & Reset Timing [AK5702] 50%DVDD VIL 2007/06 ...
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... AK5702 goes to master mode by changing M/S bit = “1”. When the AK5702 is used by master mode, LRCK and BCLK pins are a floating state until M/S bit becomes “1”. LRCK and BICK pins of the AK5702 should be pulled-down or pulled-up by the resistor (about 100kΩ) externally to avoid the floating state. When PDN pin is “ ...
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... When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the PLL3-0 and FS3-0 bits. The PLL lock time is shown in Table 4, whenever the AK5702 is supplied to a stable clocks after PLL is powered-up (PMPLL bit = “0” → “1”) or sampling frequency changes. ...
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... N/A BCLK pin LRCK pin “L” Output “L” Output Invalid Invalid See Table 10 1fs Output MCKO pin MCKO bit = “1” Invalid Invalid See Table 9 [AK5702] 2007/06 ...
Page 25
... BCLK BCLK 1fs LRCK LRCK SDTI SDTOA/B Figure 20. PLL Master Mode PS1 bit PS0 bit MCKO pin BCLK Output BCKO0 bit Frequency 0 N/A 1 32fs 0 64fs 1 N DSP or μP 256fs (default) 128fs 64fs 32fs (default) [AK5702] 2007/06 ...
Page 26
... PMADAR bit = “1” or PMADBL bit = “1” or PMADBR bit = “1”). If these clocks are not provided, the AK5702 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If the external clocks are not present, the ADC should be in the power-down mode (PMADAL= PMADAR = PMADBL = PMADBR bits = “ ...
Page 27
... EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”) When PMPLL bit is “0”, the AK5702 becomes EXT mode. Master clock is input from MCKI pin, the internal PLL circuit is not operated. This mode is compatible with I/F of the normal audio CODEC. The clocks required to operate are MCKI (256fs, 512fs or 1024fs), LRCK (fs) and BCLK (≥ ...
Page 28
... MCKI should always be present whenever the ADC is in operation (PMADAL bit = “1” or PMADAR bit = “1” or PMADBL bit = “1” or PMADBR bit = “1”). If MCKI is not provided, the AK5702 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If MCKI is not present, the ADC should be in the power-down mode (PMADAL= PMADAR = PMADBL = PMADBR bits = “ ...
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... Reserved 1 0 MSB justified compatible 0 0 Reserved 0 1 Reserved 1 0 MSB justified compatible - 29 - [AK5702] BCLK Figure 32fs Figure ≥ 32fs Figure 29 ≥ 32fs Figure 30 (default) 32fs Figure 32fs or 64fs Figure 29 32fs or 64fs Figure 30 BCLK Figure - - - - ...
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... BCLK after the rising edge (“↑”) of LRCK. MSB of SDTO is output by next falling edge (“↓”) of the rising edge (“↑”) of the first BCLK after the rising edge (“↑”) of LRCK. Table 17. Audio Interface Format in Mode [AK5702] Figure Figure 25 Figure 26 Figure 27 Figure 28 2007/06 ...
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... Lch Rch 1/ Lch Rch 1/ Lch Rch 1/fs [AK5702 2007/06 ...
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... Rch Data Rch Data 2 S compatible) [AK5702 2007/06 ...
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... Figure 34. Mode 19, 23 Timing (TDM256 mode, I MS0623-E-00 128 BCLK BCLK 16 BCLK 16 BCLK 256 BCLK BCLK 32 BCLK 32 BCLK 256 BCLK BCLK 32 BCLK 32 BCLK - 33 - [AK5702 compatible compatible) 2007/06 ...
Page 34
... Cascade TDM Mode The AK5702 supports cascading two devices in a daisy chain configuration at TDM mode. In this mode, SDTOB pin of device #1 is connected to TDMIN pin of device #2. SDTOB pin of device #2 can output 8ch TDM data multiplexed with 4ch TDM data of device #1 and 4ch TDM data of device #2. Figure 35 and Figure 37 show a connection example of a daisy chain ...
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... AK5702 #1 AK5702 #2 Figure 37. Cascade TDM Connection example (TDM256, MSB justified) LRCK BCLK(256fs) #1 SDTOB( BCLK #2 TDMIN( BCLK #2 SDTOB( L1-#2 32 BCLK MS0623-E-00 MCLK LRCK BLCK TDMIN GND SDTOA SDTOB MCLK LRCK BLCK TDMIN SDTOA SDTOB 256 BCLK ...
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... Table 21. ADCB Digital HPF Cut-off Frequency - 36 - [AK5702] ADCA Rch data All “0” (default) Rch Input Signal Lch Input Signal Rch Input Signal (L+R)/2 ADCB Rch data All “0” (default) Rch Input Signal ...
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... MIC/LINE Input Selector The AK5702 has input selector. When MDIF1 and MDIF2 bits are “0”, INAL and INAR bits select LIN1/LIN2 and RIN1/RIN2, INBL and INBR bits select LIN3/LIN4 and RIN3/RIN4 respectively. INA5L and INA5R bits also select LIN5 and RIN5, respectively. Refer to Table 24 about the typical input resistance of LIN5, RIN5. When MDIF1 and MDIF2 bits are “ ...
Page 38
... LIN4/RINB− pin MS0623-E-00 INA5L bit INAL bit MDIFA1 bit INA5R bit INAR bit MDIFA2 bit INB5L bit INBL bit MDIFB1 bit INB5R bit INBR bit MDIFB2 bit Figure 39. Mic/Line Input Selector - 38 - [AK5702] ADCA Lch ADCA Rch ADCB Lch ADCB Rch 2007/06 ...
Page 39
... MIC Gain Amplifier The AK5702 has a gain amplifier for microphone input. The gain of MIC-Amp is selected by the MGAINA1-0, MGAINB1-0 bits (Table 25). The typical input impedance of LIN1-4 and RIN1-4 is 60kΩ(typ)@MGAINA1-0, MGAINB1-0 bits = “00” or 30kΩ(typ)@MGAIN1-0 bits = “01”, “10” or “11”. Refer to Table 24 about the typical input resistance of LIN5, RIN5 ...
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... MPWRA pin LIN1 pin RIN1 pin LIN2 pin RIN2 pin LIN5 pin RIN5 pin MPWRB pin LIN3 pin RIN3 pin LIN4 pin RIN4 pin LIN5 pin RIN5 pin - 40 - [AK5702] Microphone Microphone Microphone Microphone Line Line Microphone Microphone Microphone Microphone Line Line 2007/06 ...
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... ALC Output ≥ −4.1dBFS −4.1dBFS > ALC Output ≥ −6.0dBFS −6.0dBFS > ALC Output ≥ −8.5dBFS −8.5dBFS > ALC Output ≥ −12dBFS - 41 - ALCA Operation Manual (default) 2ch Link Manual 2ch Link 4ch Link [AK5702] (default) 2007/06 ...
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... 1024ms 1 16384/fs 2048ms - 42 - 0.375dB (default) 0.750dB 1.500dB 3.000dB 0.375dB 16kHz 44.1kHz 8ms 2.9ms (default) 16ms 5.8ms 32ms 11.6ms 64ms 23.2ms 16kHz 44.1kHz 8ms 2.9ms (default) 16ms 5.8ms 32ms 11.6ms 64ms 23.2ms 128ms 46.4ms 256ms 92.9ms 512ms 185.8ms 1024ms 371.5ms [AK5702] 2007/06 ...
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... Table 32. ALC Recovery GAIN Step GAIN(dB) Step +36.0 +35.625 +35.25 : +30.375 0.375dB +30.0 +29.625 : −53.25 −53.625 −54.0 MUTE RFSTA/B0 bit Recovery Speed 0 4 times 1 8 times 0 16times 1 N/A Table 34. Fast Recovery Speed Setting - 43 - [AK5702] (default) (default) (default) 2007/06 ...
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... Enable 1 Enable Example: Limiter = Zero crossing Enable Recovery Cycle = 16ms@8kHz Limiter and Recovery Step = 1 Maximum Gain = +30.0dB Limiter Detection Level = −4.1dBFS Fast Limiter Operation :ON ALCA bit = “1” (1) Addr=08H&09H, Data=91H (2) Addr=0AH, Data=00H (3) Addr=0BH, Data=E1H (4) Addr=0DH, Data=02H (5) Addr=0CH, Data=81H [AK5702] 2007/06 ...
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... ADC initialization cycle after PMADA/BL or PMADA/BR bit is changed to “1”. IVA/BL7-0 IVA/BR7-0 F1H F0H EFH : 92H 91H 90H : 03H 02H 01H 00H MS0623-E-00 GAIN (dB) Step +36.0 +35.625 +35.25 : +0.375 0.375dB 0.0 −0.375 : −53.25 −53.625 −54 MUTE Table 36. Input Digital Volume Setting - 45 - [AK5702] (default) 2007/06 ...
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... ALCA/B bit = “0”. MS0623-E-00 Disable Enable E1H(+30dB) C6H(+20dB) E1H(+30dB) E1(+30dB) --> F1(+36dB) (1) C6H(+20dB) E1(+30dB) --> F1(+36dB) Figure 44. IVOL value during 2ch ALC operation - 46 - [AK5702] Disable E1(+30dB) (2) C6H(+20dB) 2007/06 ...
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... ADCB is powered down by setting PMADBL bit or PMADBR bit “0”. (7) ADCA is powered down by setting PMADAL bit or PMADAR bit “0”. MS0623-E-00 (3) (4) (4) 4ch Link ALC Manual Mode 4ch Link ALC Manual Mode Figure 45. 4ch Link ALC Mode sequence - 47 - [AK5702] (5) (7) (6) (4) (4) Manual Mode Power Down Manual Mode Power Down 2007/06 ...
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... System Reset Upon power-up, the AK5702 should be reset by bringing the PDN pin = “L”. This ensures that all internal registers reset to their initial values. The ADC enters an initialization cycle that starts when the PMADAL or PMADAR or PMADBL or PMADBR bit is changed from “0” to “1”. The initialization cycle time is 3088/fs=70.0ms@fs=44.1kHz when HPF1-0 bits are “00” (Table 37). During the initialization cycle, the ADC digital data outputs of both channels are forced to a 2’ ...
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... READ/WRITE (“1”: WRITE, “0”: READ); Fixed to “1” Register Address Figure 46. Serial Control I/F Timing - Clock, “H” or “L” “H” or “L” [AK5702] 2007/06 ...
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... HIGH defines a STOP condition (Figure 53). The AK5702 can perform more than one byte write operation per sequence. After the receipt of the third byte the AK5702 generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred ...
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... READ Operations Set the R/W bit = “1” for the READ operation of the AK5702. After transmission of data, the master can read the next address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word. After receiving each data packet the internal 6-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 1CH prior to generating a stop condition, the address counter will “ ...
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... MASTER S START CONDITION SDA SCL MS0623-E-00 S Figure 53. START and STOP Conditions 2 1 Figure 54. Acknowledge on the I data line change stable; of data data valid allowed Figure 55. Bit Transfer on the stop condition not acknowledge acknowledge 8 clock pulse for acknowledgement 2 C-Bus 2 C-Bus [AK5702] 9 2007/06 ...
Page 53
... IVBL3 IVBL2 IVBL1 IVBR3 IVBR2 IVBR1 ZTMB1 ZTMB0 WTMB1 REFB3 REFB2 REFB1 RGB1 RGB0 LMTHB1 [AK5702] D0 PMADAL PMPLL INAL MGAINA0 DIF0 FS0 PS0 0 IVOLAC IVAL0 IVAR0 WTMA0 REFA0 LMTHA0 ALC4 PMADBL 0 0 INBL MGAINB0 ...
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... PLL3-0: PLL Reference Clock Select (Table 4) Default: “1001” (MCKI pin=12MHz) MS0623-E- PLL3 PLL2 PMVCM PMADAR PLL1 PLL0 M [AK5702] D0 PMADAL 0 D0 PMPLL 0 2007/06 ...
Page 55
... Mic Gain Control Default MGAINA1-0: MIC-AmpA Gain Control (Table 25) Default: “01” (+15dB) MS0623-E- INA5R INA5L PMMPA [AK5702 INAR INAL MDIFA2 MDIFA1 MGAINA1 MGAINA0 2007/ ...
Page 56
... HPFA1 HPFA0 BCKO1 BCKO0 INCA MSBS BCKP DIF1 FS3 FS2 FS1 MCKO PS1 [AK5702] D0 DIF0 1 D0 FS0 1 D0 PS0 0 2007/06 ...
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... REFA4 IVAL3 IVAL2 IVAL1 IVAR3 IVAR2 IVAR1 ZTMA1 ZTMA0 WTMA1 REFA3 REFA2 REFA1 [AK5702] D0 IVOLAC 1 D0 IVAL0 IVAR0 1 D0 WTMA0 0 D0 REFA0 1 2007/06 ...
Page 58
... ZELMNA LMATA1 LMATA0 TE3 TE2 TE1 TE0 RGA1 RGA0 LMTHA1 LFST TMASTER [AK5702] D0 LMTHA0 0 D0 ALC4 2007/06 ...
Page 59
... INB5R INB5L PMMPB PMADBR INBR MDIFB2 MDIFB1 MGAINB1 [AK5702] D0 PMADBL 0 D0 INBL 0 D0 MGAINB0 1 2007/06 ...
Page 60
... IVBL3 IVBL2 IVBL1 IVBR3 IVBR2 IVBR1 [AK5702 IVOLBC 1 D0 IVBL0 IVBR0 1 2007/06 ...
Page 61
... REFB7 REFB6 REFB5 REFB4 ALCB ZELMNB LMATB1 LMATB0 ZTMB1 ZTMB0 WTMB1 REFB3 REFB2 REFB1 RGB1 RGB0 LMTHB1 [AK5702] D0 WTMB0 0 D0 REFB0 1 D0 LMTHB0 0 2007/06 ...
Page 62
... All digital input pins should not be left floating. - When the AK5702 is EXT mode (PMPLL bit = “0”), a resistor and capacitor of VCOC pin is not needed. - When the AK5702 is PLL mode (PMPLL bit = “1”), a resistor and capacitor of VCOC pin is shown in Table 4. 0 parallel with Cp+Rp improves PLL jitter characteristics. ...
Page 63
... All digital input pins should not be left floating. - When the AK5702 is EXT mode (PMPLL bit = “0”), a resistor and capacitor of VCOC pin is not needed. - When the AK5702 is PLL mode (PMPLL bit = “1”), a resistor and capacitor of VCOC pin is shown in Table 4. 0 parallel with Cp+Rp improves PLL jitter characteristics. ...
Page 64
... VSS1 and VSS2 of the AK5702 should be distributed separately from the ground of external controllers. - All digital input pins should not be left floating. - When the AK5702 is EXT mode (PMPLL bit = “0”), a resistor and capacitor of VCOC pin is not needed. Figure 58. Typical Connection Diagram (Cascode TDM) ...
Page 65
... If AVDD and DVDD are supplied separately, the power-up sequence is not critical. VSS1 and VSS2 of the AK5702 should be connected to the analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. ...
Page 66
... PLL operation starts after PMPLL bit changes from “0” to “1” and MCKI is supplied from an external source. PLL lock time is 40ms(max) at MCKI=12MHz (Table 4). (6) The AK5702 starts to output the LRCK and BCLK clocks after the PLL becomes stable. Then normal operation starts. ...
Page 67
... Internal Clock <Example> (1) After Power Up: PDN pin “L” → “H” “L” time of 150ns or more is needed to reset the AK5702. (2) DIF1-0, FS3-0 and PLL3-0 bits should be set during this period. (3) Power Up VCOM: PMVCM bit = “0” → “1” VCOM should first be powered up before the other block operates. ...
Page 68
... LRCK pin <Example> (1) After Power Up: PDN pin “L” → “H” “L” time of 150ns or more is needed to reset the AK5702. (2) DIF1-0, PLL3-0, FS3-0, BCKO1-0 and M/S bits should be set during this period. (3) Power Up VCOM: PMVCM bit = “0” → “1” ...
Page 69
... BCLK pin <Example> (1) After Power Up: PDN pin “L” → “H” “L” time of 150ns or more is needed to reset the AK5702. (2) DIF1-0 and FS1-0 bits should be set during this period. (3) Power Up VCOM: PMVCM bit = “0” → “1” VCOM should first be powered up before the other block operates. ...
Page 70
... LRCK pin <Example> (1) After Power Up: PDN pin “L” → “H” “L” time of 150ns or more is needed to reset the AK5702. (2) DIF1-0, FS1-0, BCKO1-0, M/S, TE3-0 and TMASTER bits should be set during this period as follows. (2a) M/S bit = “1”, setting of FS3-0 and BCKO1-0 bits. ...
Page 71
... This sequence is an example of ALCA setting at fs=44.1kHz. If the parameter of the ALCA is changed, please refer to Figure 43. At first, clocks should be supplied according to “Clock Set Up” sequence. (1) Set up a sampling frequency (FS3-0 bit). When the AK5702 is PLL mode, MIC and ADCA should be powered-up in consideration of PLL lock time after a sampling frequency is changed. (2) Set up MIC input (Addr: 02H&03H) ...
Page 72
... BCLK frequency at Master Mode: 64fs Input Master Clock Select at PLL Mode: 11.2896MHz Sampling Frequency: 44.1kHz (1) Addr:01H, Data:10H (2) Addr:06H, Data:00H (3) Stop an external MCKI Example Audio I/F Format : I2S PLL Reference clock: BCLK BCLK frequency: 64fs Sampling Frequency: 44.1kHz (1) Addr:01H, Data:0CH (2) Stop the external clocks [AK5702] 2007/06 ...
Page 73
... BCLK frequency: 64fs Sampling Frequency: 44.1kHz (1) Addr:01H, Data:10H (2) Addr:06H, Data:00H (3) Stop the external clocks Example Audio I/F Format :I2S Input MCKI frequency:256fs Sampling Frequency:44.1kHz (1) Stop the external clocks Example Audio I/F Format :I2S Input MCKI frequency:256fs Sampling Frequency:44.1kHz (1) Stop MCKI [AK5702] 2007/06 ...
Page 74
... If the clocks are supplied, power down VCOM (PMVCM bit: “1” → “0”) after all blocks except for VCOM are powered-down and a master clock stops. The AK5702 is also powered-down by PDN pin = “L”. When PDN pin = “L”, the registers are initialized. ...
Page 75
... Note) The exposed pad on the bottom surface of the package must be open or connected to the ground. ■ Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: MS0623-E-00 PACKAGE 0.40 ± 0. C0. Epoxy Cu Solder (Pb free) plate - 75 - [AK5702] Exposed Pad 32 1 3.5 2007/06 ...
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... MS0623-E-00 MARKING AKM AK5702 XXXXX 1 XXXXX: Date code identifier (5digits) REVISION HISTORY Reason Page Contents First Edition IMPORTANT NOTICE , and AKEMD assumes no responsibility for such use, except for the use Note2 [AK5702] in any safety, life support, or Note1) 2007/06 ...