x5043s8c1038 Intersil Corporation, x5043s8c1038 Datasheet - Page 8

• Manufacturer Part Number: x5043s8c1038
• Description: Cpu Supervisor With 4k Spi Eeprom
• Manufacturer: Intersil Corporation

Note:
INSTRUCTION NAME
New V
Old V
Error ≤ -Emax
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
- Error
CC
WRITE
FIGURE 4. V
WREN
WRSR
CC
RSDR
READ
WRDI
=
Applied
Applied
NO
Emax = Maximum Desired Error
Set V
TRIP
V
(V
TRIP
Apply 5V to V
Decrement V
CC
Measured V
Desired V
-Desired V
CC
PROGRAMMING SEQUENCE
goes active?
INSTRUCTION FORMAT*
Reset V
RESET pin
Sequence
Sequence
Set V
= V
Execute
Execute
Programming
= V
DONE
CC
8
CC
TRIP
0000 A
0000 A
YES
-Emax < Error < Emax
0000 0100
0000 0101
0000 0001
–10mV)
0000 0110
TRIP
Applied =
TRIP
TRIP
TRIP
CC
CC
8
8
010
011
New V
Old V
Error ≥ Emax
Reset V
Sequence
Execute
- Error
CC
CC
=
TABLE 1. INSTRUCTION SET
Set the Write Enable Latch (Enable Write Operations)
Reset the Write Enable Latch (Disable Write Operations)
Read Status Register
Write Status Register (Watchdog and Block Lock)
Read Data from Memory Array Beginning at Selected Address
Write Data to Memory Array Beginning at Selected Address (1 to 16 bytes)
Applied
Applied
TRIP
X5043, X5045
SPI Serial Memory
The memory portion of the device is a CMOS Serial
EEPROM array with Intersil’s block lock protection. The array
is internally organized as 512 x 8 bits. The device features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.
The device utilizes Intersil’s proprietary Direct Write
providing a minimum endurance of 1,000,000 cycles and a
minimum data retention of 100 years.
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families.
The device contains an 8-bit instruction register that controls
the operation of the device. The instruction code is written to
the device via the SI input. There are two write operations
that requires only the instruction byte. There are two read
operations that use the instruction byte to initiate the output
of data. The remainder of the operations require an
instruction byte, an 8-bit address, then data bytes. All
instruction, address and data bits are clocked by the SCK
input. All instructions (Table 1), addresses and data are
transferred MSB first.
Clock and Data Timing
Data input on the SI line is latched on the first rising edge of
SCK after CS goes LOW. Data is output on the SO line by
the falling edge of SCK. SCK is static, allowing the user to
stop the clock and then start it again to resume operations
where left off. CS must be LOW during the entire operation.
OPERATION
March 16, 2006
™
FN8126.2
cell,