ts32mls64v6d Transcend Information. Inc., ts32mls64v6d Datasheet - Page 9

• Manufacturer Part Number: ts32mls64v6d
• Description: 168pin Pc133 Unbuffered Dimm 256mb With 16mx8 Cl3 Placement
• Manufacturer: Transcend Information. Inc.

Transcend Information Inc.
SIMPLIFIED TRUTH TABLE
T
Register
Refresh
Bank Active & Row Addr.
Read &
Column Address
Write &
Column Address
Burst Stop
Precharge
Clock Suspend or
Active Power
Down
Precharge Power
Down Mode
DQM
No Operation Command
Note:
T
T
S
S
S
3
3
3
1. OP Code: Operand Code
2. MRS can be issued only at both banks precharge state.
3. Auto refresh functions are as same as CBR refresh of DRAM.
4. BA
5. During burst read or write with auto precharge, new read/write command cannot be issued.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edged of a CLK masks the data-in at the very CLK (Write DQM latency is 0),
2
2
2
A
A new command can be issued after 2 CLK cycles of MRS.
The automatically precharge without row precharge command is meant by “Auto”.
Auto/self refresh can be issued only at both banks precharge state.
If both BA
If both BA
If both BA
If both BA
If A
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
0
~A
M
M
0
COMMAND
M
10
~BA
11
/AP is “High” at row precharge, BA
Mode Register Set
Auto Refresh
Self
Refresh
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
Bank Selection
Both Banks
, BA
L
1
L
L
: Bank select address.
0
0
0
0
0
and BA
and BA
is “Low” and BA
is “High” and BA
~BA
S
S
S
Entry
Entry
1
6
Exit
Exit
6
6
: Program keys. (@MRS)
1
1
are “Low” at read, write, row active and precharge, bank A is selected.
are “High” at read, write, row active and precharge, bank D is selected.
4
4
4
Entry
Exit
V
V
V
1
1
is “High” at read, write, row active and precharge, bank B is selected.
6
6
is “Low” at read, write, row active and precharge, bank C is selected.
6
D
D
CKEn-1 CKEn
D
H
H
H
H
H
H
H
H
H
H
H
L
L
L
0
and BA
H
H
H
H
X
L
X
X
X
X
X
L
L
X
1
are ignored and both banks are selected.
/CS
H
H
X
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
9
/RAS
H
X
H
H
H
X
V
X
X
H
X
V
X
X
H
L
L
L
L
/CAS
H
X
H
H
H
X
V
X
X
H
X
V
X
H
L
L
L
L
/WE
(V=Valid, X=Don’t Care, H=Logic High, L=Logic Low)
168PIN PC133 Unbuffered DIMM
H
H
X
H
H
X
V
X
X
H
X
V
X
H
L
L
L
L
DQM
X
X
X
X
X
X
X
X
X
X
X
X
V
X
256MB With 16Mx8 CL3
BA
V
V
V
V
X
0,1
OP CODE
A
10
H
H
H
Row Address
L
L
L
/AP A
X
X
X
X
X
X
X
11
Address
Address
Column
Column
(A
(A
, A
0
0
X
~A
~A
0
9
9
~A
)
)
9
Note
4, 5
4, 5
1,2
3
3
3
3
4
4
6
7